Spike anneal qualification for 0.13 μm USJ technology on Radiance/spl trade/ Centura/spl reg/

2002 ◽  
Author(s):  
H.L. Sun ◽  
H.M. Jao ◽  
H.T. Huang ◽  
J.Y. Pan ◽  
T.H. Hou ◽  
...  
Keyword(s):  
Spike Anneal

Phosphorus Implant For S/D Extension Formation: Diffusion And Activation Study After Spacer And Spike Anneal

2006 ◽  
Author(s):  
S. H. Yeong ◽  
B. Colombeau ◽  
F. Benistant ◽  
M. P. Srinivasan ◽  
C. P. A. Mulcahy ◽  
...  
Keyword(s):  
Spike Anneal

Implant Annealing – An Evolution from Soak over Spike to Millisecond Annealing

2008 ◽  
Vol 573-574 ◽  
pp. 207-228 ◽  
Author(s):  
Silke Paul ◽  
Wilfried Lerch
Keyword(s):  
Process Parameters ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Peak Temperature ◽  
Historical Overview ◽  
Temperature Ramp ◽  
Stabilization Temperature ◽  
Spike Anneal

This work presents a summary on the use of rapid thermal processing for implant annealing. It gives a short historical overview of rapid thermal processing systems and the first implant anneal processes on these newly developed tools. We then looked in detail on the soak anneal and spike anneal processes and the influence of certain process parameters. For the soak anneal influences of the ambient, either oxidizing or nitriding, were evaluated. The results of spike anneal processes are influenced by the pre-stabilization temperature, ramp-up and ramp-down rate, peak temperature, and gaseous ambient. The need for shallow, abrupt and highly activated junctions leads to co-implantation of species like fluorine or carbon in conjunction with pre-amorphization. Nowadays, combinations of spike and millisecond annealing as well as millisecond annealing alone are in the focus.

The Effect of Oxide Trenches on Defect Formation and Evolution in Ion-Implanted Silicon

2004 ◽  
Vol 810 ◽  
Author(s):  
Nina Burbure ◽  
Kevin S. Jones
Keyword(s):  
Silicon Oxide ◽  
Defect Formation ◽  
Solid Phase ◽  
Amorphous Layer ◽  
Oxide Interface ◽  
Cross Sectional ◽  
Patterned Wafers ◽  
Edge Defects ◽  
Formation And Evolution ◽  
Spike Anneal

ABSTRACTPattern induced defects during advanced CMOS processing can lead to lower quality devices with high leakage currents. Within this study, the effects of oxide trenches on implant related defect formation and evolution in silicon patterned wafers is examined. Oxide filled trenches approximately 4000Å deep were patterned into 300 mm <100> silicon wafers. Patterning was followed by ion implantation of Si+ at energies ranging from 10 to 80 keV. Samples were amorphized with doses of 1×1015 atoms/cm2, 5×1015 atoms/cm2, and 1×1016 atoms/cm2. Two independent repeating structures were studied. The first structure is comprised of silicon oxide filled trench lines, 3.7μm wide spaced 12.5μm apart, while the second structure contains silicon squares, 0.6μm on a side, surrounded by a silicon oxide filled trench. Cross- sectional and planar view transmission electron microscopy (TEM) samples were used to examine the defect morphology after annealing at temperatures ranging from 700°C to 950°C and at times between 1 second and 1 minute. Following complete regrowth, an array of defects was observed to form near the surface at the silicon/silicon oxide interface. These trench edge defects appeared to nucleate at the amorphous-crystalline interface for all energies and doses studied. Upon a spike anneal at 700°C, it was observed that regrowth of the amorphous layer had completed except in the region near the trench edge. Thus, it is believed that this defect results from the pinning of the amorphous-crystalline interface along the trench edge during solid phase epitaxial regrowth (SPER).

Investigation of Laser Spike Anneal Dwell Time and It's Compatibility with Embedded-SiGe

2019 ◽  
Vol 34 (1) ◽  
pp. 737-742
Author(s):  
Yonggen He ◽  
Yong Chen ◽  
Jiongping Lu ◽  
Jingang Wu ◽  
Chuanjin Xu ◽  
...  
Keyword(s):  
Dwell Time ◽  
Spike Anneal

Model Based Temperature Control in RTP Yielding ±0.1 °C accuracy on A 1000 °C, 2 second, 100 °C/s Spike Anneal

1998 ◽  
Vol 525 ◽  
Author(s):  
Peter Vandenabeele ◽  
Wayne Renken
Keyword(s):  
Differential Equations ◽  
Temperature Control ◽  
Control Method ◽  
Nonlinear Differential Equations ◽  
System Response ◽  
Model Based Control ◽  
First Order ◽  
Model Based ◽  
Measured System ◽  
Spike Anneal

ABSTRACTA Model Based Control method is presented for accurate control of RTP systems. The model uses 4 states: lamp filament temperature, wafer temperature, quartz temperature and TC temperature. A set of 4 first order, nonlinear differential equations describes the model. Feedback is achieved by updating the model, based on a comparison between actual (measured) system response and modeled system response.

Spike Anneal Optimization for Digital and Analogue High Performance 0.13 um CMOS Platform

2002 ◽  
Author(s):  
E. Josse ◽  
F. Arnaud ◽  
F. Wacquant ◽  
D. Lenoble ◽  
O. Menut ◽  
...  
Keyword(s):  
High Performance ◽  
Spike Anneal

Widening of FUSI RTP Process Window by Spike Anneal

2007 ◽  
Author(s):  
A. Lauwers ◽  
S. Mertens ◽  
P. Absil ◽  
T. Chiarella ◽  
T. Hoffmann ◽  
...  
Keyword(s):  
Process Window ◽  
Spike Anneal
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