New latchup failure mechanism induced by an elevated via resistance on multilayer CMOS technology

Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology

13th International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2006.251045 ◽

2006 ◽

Cited By ~ 12

Author(s):

Junjun Li ◽

David Alvarez ◽

Kiran Chatty ◽

Michel Abou-khalil ◽

Robert Gauthier ◽

...

Keyword(s):

Failure Mechanism ◽

Cmos Technology

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A new failure mechanism on analog I/O cell under ND-mode esd stress in deep-submicron CMOS technology

Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005. ◽

10.1109/ipfa.2005.1469163 ◽

2005 ◽

Cited By ~ 1

Author(s):

Shih-Hung Chen ◽

Ming-Dou Ker ◽

Che-Hao Chuang

Keyword(s):

Failure Mechanism ◽

Cmos Technology ◽

Deep Submicron ◽

Submicron Cmos

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New Latchup Failure Mechanism Induced by an Elevated Via Resistance on Multilayer CMOS Technology

33rd IEEE International Reliability Physics Symposium ◽

10.1109/irps.1995.363704 ◽

1995 ◽

Author(s):

Yuan-Chuan Steven Chen ◽

Sam Hu ◽

Tom J. DeBonis

Keyword(s):

Failure Mechanism ◽

Cmos Technology

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NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-μm CMOS technology

IEEE Transactions on Device and Materials Reliability ◽

10.1109/tdmr.2002.1014666 ◽

2002 ◽

Vol 2 (1) ◽

pp. 2-8 ◽

Cited By ~ 10

Author(s):

A. Salman ◽

R. Gauthier ◽

W. Stadler ◽

K. Esmark ◽

M. Muhammad ◽

...

Keyword(s):

Failure Mechanism ◽

Cmos Technology ◽

Protection Strategy ◽

Self Protection

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On the role of tin underlays for the prevention of thermal grooving in thin gold films

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100145030 ◽

1986 ◽

Vol 44 ◽

pp. 732-733

Author(s):

Jin Young Kim ◽

R. E. Hummel ◽

R. T. DeHoff

Keyword(s):

Thin Film ◽

Free Surface ◽

Grain Boundary ◽

Beneficial Effect ◽

Failure Mechanism ◽

Failure Mechanisms ◽

Distinct Advantage ◽

Gold Films ◽

Gold Thin Film

Gold thin film metallizations in microelectronic circuits have a distinct advantage over those consisting of aluminum because they are less susceptible to electromigration. When electromigration is no longer the principal failure mechanism, other failure mechanisms caused by d.c. stressing might become important. In gold thin-film metallizations, grain boundary grooving is the principal failure mechanism.Previous studies have shown that grain boundary grooving in gold films can be prevented by an indium underlay between the substrate and gold. The beneficial effect of the In/Au composite film is mainly due to roughening of the surface of the gold films, redistribution of indium on the gold films and formation of In2O3 on the free surface and along the grain boundaries of the gold films during air annealing.

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