Impact of strained-Si PMOS transistors on SRAM soft error rates

2011 ◽  
Author(s):  
N. N. Mahatme ◽  
B. L. Bhuva ◽  
Y-P Fang ◽  
A. S. Oates
Keyword(s):  
Error Rates ◽  
Soft Error ◽  
Strained Si

Impact of Strained-Si PMOS Transistors on SRAM Soft Error Rates

2012 ◽  
Vol 59 (4) ◽  
pp. 845-850 ◽  
Author(s):  
Nihaar N. Mahatme ◽  
Bharat L. Bhuva ◽  
Yi-Pin Fang ◽  
Anthony S. Oates
Keyword(s):  
Error Rates ◽  
Soft Error ◽  
Strained Si

STRADDLE-GATE TRANSISTOR: A MOSFET IN THE LIMIT OF USEFUL FIELD-EFFECT

2000 ◽  
Vol 10 (01) ◽  
pp. 231-245 ◽  
Author(s):  
SANDIP TIWARI ◽  
A. KUMAR ◽  
J. J. WELSER
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Oxide Thickness ◽  
Error Rates ◽  
Soft Error ◽  
The Other ◽  
Power Gain ◽  
Virtual Source ◽  
Effect Transistor ◽  
Output Conductance

For transistor, the limit of usable field-effect is defined by tunneling between the source and the drain - the mechanism that competes with field-effect as device dimensions shrink to near deBroglie wavelength. This is a more fundamental constraint in the operation of a field-effect transistor than random dopants, oxide thickness, doping magnitudes and depth, gate resistivity, soft-error rates, etc. We describe here a MOSFET structure, the straddle-gate transistor, that uses inversion regions as virtual source and drain, operates within the limits placed by the other constraints, and operates at acceptable power levels with good power gain and output conductance at 10 nm channel lenth. Experimental behavior of the straddle geometry are also described to summarized the advantages accrued using electron injection from the thin inversion regions.

Parametric Influences on System Soft Error Rates

1980 ◽  
Author(s):  
John W. Peeples ◽  
Thomas J. Every
Keyword(s):  
Error Rates ◽  
Soft Error
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