A gated clock scheme for low power scan-based BIST

2002 ◽  
Author(s):  
Y. Bonhomme ◽  
P. Girard ◽  
L. Guiller ◽  
C. Landrault ◽  
S. Pravossoudovitch
Keyword(s):  
Low Power ◽  
Gated Clock

A gated clock scheme for low power scan testing of logic ICs or embedded cores

2002 ◽  
Author(s):  
Y. Bonhomme ◽  
P. Girard ◽  
L. Guiller ◽  
C. Landrault ◽  
S. Pravossoudovitch
Keyword(s):  
Low Power ◽  
Scan Testing ◽  
Embedded Cores ◽  
Gated Clock

A Gated Clock Scheme for Low Power Testing of Logic Cores

2006 ◽  
Vol 22 (1) ◽  
pp. 89-99 ◽  
Author(s):  
Yannick Bonhomme ◽  
Patrick Girard ◽  
Loïs Guiller ◽  
Christian Landrault ◽  
Serge Pravossoudovitch ◽  
...  
Keyword(s):  
Low Power ◽  
Low Power Testing ◽  
Power Testing ◽  
Gated Clock
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