A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques

<span>A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.</span>

Performance Evaluation of Ring Counter using Gated Clock

Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is a tremendous reduction in the chip size. Minimum power consumption has become a priority.In this paper, we propose a low power design techniquefor Ring counter using gated clock.In this paper, we demonstrate the working of ring counter using gated clock.The results are illustrated in Xilinx. The simulation results and the synthesis outputis shown.