A gated clock scheme for low power scan testing of logic ICs or embedded cores

2002 ◽  
Author(s):  
Y. Bonhomme ◽  
P. Girard ◽  
L. Guiller ◽  
C. Landrault ◽  
S. Pravossoudovitch
Keyword(s):  
Low Power ◽  
Scan Testing ◽  
Embedded Cores ◽  
Gated Clock

A gated clock scheme for low power scan-based BIST

2002 ◽  
Author(s):  
Y. Bonhomme ◽  
P. Girard ◽  
L. Guiller ◽  
C. Landrault ◽  
S. Pravossoudovitch
Keyword(s):  
Low Power ◽  
Gated Clock

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing

2018 ◽  
Author(s):  
Yucong Zhang ◽  
Xiaoqin Wen ◽  
Stefan Holst ◽  
Kohei Miyase ◽  
Seiji Kajihara ◽  
...  
Keyword(s):  
Low Power ◽  
Clock Skew ◽  
Scan Testing ◽  
Scan Chain

TRP for Low-Power Scan Testing

2002 ◽  
pp. 203-216
Author(s):  
Krishnendu Chakrabarty ◽  
Vikram Iyengar ◽  
Anshuman Chandra
Keyword(s):  
Low Power ◽  
Scan Testing
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