SRAM Design Techniques for Sub-nano CMOS Technology

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65nm FD-SOI/SON CMOS technology

Microelectronics Journal ◽

10.1016/j.mejo.2014.04.032 ◽

2014 ◽

Vol 45 (7) ◽

pp. 848-856 ◽

Cited By ~ 6

Author(s):

Deepon Saha ◽

Subir Kumar Sarkar

Keyword(s):

Low Power ◽

High Speed ◽

Memory Cell ◽

Cmos Technology ◽

Cell Design ◽

Sram Memory ◽

Design Techniques

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A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2009.2034082 ◽

2010 ◽

Vol 45 (1) ◽

pp. 103-110 ◽

Cited By ~ 32

Author(s):

Yih Wang ◽

Uddalak Bhattacharya ◽

Fatih Hamzaoglu ◽

Pramod Kolar ◽

Yong-Gee Ng ◽

...

Keyword(s):

Power Management ◽

Cmos Technology ◽

Metal Gate ◽

High K ◽

Sram Design

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A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2007.907996 ◽

2008 ◽

Vol 43 (1) ◽

pp. 172-179 ◽

Cited By ~ 49

Author(s):

Yih Wang ◽

Hong Jo Ahn ◽

Uddalak Bhattacharya ◽

Zhanping Chen ◽

Tom Coan ◽

...

Keyword(s):

Low Power ◽

Mobile Applications ◽

Cmos Technology ◽

Ultra Low Power ◽

Leakage Reduction ◽

Sram Design ◽

Low Power Cmos

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The effects of total ionizing dose irradiation on CMOS technology and the use of design techniques to mitigate total dose effects

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320) ◽

10.1109/relphy.2002.996663 ◽

2003 ◽

Cited By ~ 5

Author(s):

R.C. Lacoe

Keyword(s):

Total Dose ◽

Cmos Technology ◽

Total Ionizing Dose ◽

Dose Irradiation ◽

Dose Effects ◽

Total Dose Effects ◽

Design Techniques

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Novel 10-T Write Driver SRAM Design Using 45 nm CMOS Technology with Leakage Current Reduction Scheme for FPGA Routing Switch Architecture

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2018.2252 ◽

2018 ◽

Vol 13 (5) ◽

pp. 775-787 ◽

Cited By ~ 1

Author(s):

S. Lakshmi Narayanan ◽

Reeba Korah ◽

A. Swarnalatha

Keyword(s):

Leakage Current ◽

Cmos Technology ◽

Reduction Scheme ◽

Switch Architecture ◽

Sram Design ◽

Current Reduction

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SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) ◽

10.1109/vlsic.2004.1346592 ◽

2004 ◽

Cited By ~ 44

Author(s):

K. Zhang ◽

U. Bhattacharya ◽

Z. Chen ◽

F. Hamzaoglu ◽

D. Murray ◽

...

Keyword(s):

Cmos Technology ◽

Reduction Scheme ◽

Leakage Reduction ◽

Sram Design

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Ultralow power SRAM design in near threshold region using 45nm CMOS technology

2011 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY ◽

10.1109/eit.2011.5978606 ◽

2011 ◽

Cited By ~ 2

Author(s):

Yinhui Chen ◽

Zhiyuan Yu ◽

Haiqing Nan ◽

Ken Choi

Keyword(s):

Cmos Technology ◽

Threshold Region ◽

Sram Design ◽

Ultralow Power ◽

Near Threshold

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Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology

Advanced VLSI Design and Testability Issues ◽

10.1201/9781003083436-14 ◽

2020 ◽

pp. 233-250

Author(s):

Yelithoti Sravana Kumar ◽

Tapaswini Samant ◽

Swati Swayamsiddha

Keyword(s):

Low Power ◽

Circuit Design ◽

Power Efficiency ◽

Cmos Technology ◽

Efficiency Analysis ◽

Power Circuit ◽

Design Techniques

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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2012.2213513 ◽

2013 ◽

Vol 48 (1) ◽

pp. 150-158 ◽

Cited By ~ 46

Author(s):

Eric Karl ◽

Yih Wang ◽

Yong-Gee Ng ◽

Zheng Guo ◽

Fatih Hamzaoglu ◽

...

Keyword(s):

Cmos Technology ◽

Sram Design

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A new write assist technique for SRAM design in 65 nm CMOS technology

Integration ◽

10.1016/j.vlsi.2015.01.001 ◽

2015 ◽

Vol 50 ◽

pp. 16-27 ◽

Cited By ~ 8

Author(s):

Hooman Farkhani ◽

Ali Peiravi ◽

Farshad Moradi

Keyword(s):

Cmos Technology ◽

Sram Design

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