High Gamma Value 3D-Stackable HK/MG-Stacked Tri-Gate Nanowire Poly-Si FETs With Embedded Source/Drain and Back Gate Using Low Thermal Budget Green Nanosecond Laser Crystallization Technology

2016 ◽  
Vol 37 (5) ◽  
pp. 533-536 ◽  
Author(s):  
Chih-Chao Yang ◽  
W.-H. Huang ◽  
T.-Y. Hsieh ◽  
Tsung-Ta Wu ◽  
Hsing-Hsiang Wang ◽  
...  
Keyword(s):  
Nanosecond Laser ◽  
Laser Crystallization ◽  
Back Gate ◽  
Thermal Budget ◽  
High Gamma ◽  
Low Thermal Budget

scholarly journals Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Micromachines ◽  
2020 ◽  
Vol 11 (8) ◽  
pp. 741
Author(s):  
Tung-Ying Hsieh ◽  
Ping-Yi Hsieh ◽  
Chih-Chao Yang ◽  
Chang-Hong Shen ◽  
Jia-Min Shieh ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Laser Annealing ◽  
Three Dimensional ◽  
Far Infrared ◽  
Superior Performance ◽  
Nanosecond Laser ◽  
Thermal Budget ◽  
Si Nanowire ◽  
Single Grain ◽  
Low Thermal Budget

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

2010 ◽  
Vol 16 (1) ◽  
pp. 106-113 ◽  
Author(s):  
Kah-Wee Ang ◽  
Tsung-Yang Liow ◽  
Ming-Bin Yu ◽  
Qing Fang ◽  
Junfeng Song ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget ◽  
Low Thermal Budget

Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration

2018 ◽  
Author(s):  
Zhicheng Wu ◽  
Jacopo Franco ◽  
Anne Vandooren ◽  
Ben Kaczer ◽  
Philippe Roussel ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Low Thermal Budget

Low Thermal Budget Crystallization of Amorphous Silicon by Nanoclusters

2009 ◽  
Vol 12 (9) ◽  
pp. H319 ◽  
Author(s):  
Il-Suk Kang ◽  
Sung-Hun Yu ◽  
Hyun-Sang Seo ◽  
Jeong-Hun Kim ◽  
Jun-Mo Yang ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Thermal Budget ◽  
Low Thermal Budget

Implementation of Wafer Level Packaging KOZ using SU-8 as Dielectric for the Merging of WL Fan Out to Microfluidic and Biomedical Applications

2017 ◽  
Vol 2017 (1) ◽  
pp. 000569-000575 ◽  
Author(s):  
André Cardoso ◽  
Raquel Pinto ◽  
Elisabete Fernandes ◽  
Steffen Kroehnert
Keyword(s):  
Biomedical Applications ◽  
Microfluidic Channel ◽  
Cost Effective ◽  
Curing Temperature ◽  
Microfluidic Channels ◽  
Wafer Level ◽  
Thermal Budget ◽  
Chip Area ◽  
Wide Range ◽  
Low Thermal Budget

Abstract Due to its versatility for high density, heterogeneous integration, Wafer Level Fan Out (WLFO) packaging has recently seen a tremendous growth in a broad array of applications, from telecommunications and automotive, to optical and environmental sensing, while addressing the challenges of the next big wave of the Internet of Things (IoT). In this context, WLFO is continuously being challenged to include new families of MEMS/NEMS/MOEMS sensors, low thermal budget devices and biochips with microfluidics for biomedical applications. Recent developments in WLFO technology by NANIUM [1] demonstrated the implementation of a keep-out-zone (KOZ) mechanism intended to 1st) protect sensitive sensor areas during the backend processing of WLFO wafers and 2nd) create open zones on the Re-Distribution Layers (RDL). This way, the KOZ mechanism provides a physical, direct path from the embedded device to the environment. This is a necessary feature for environment sensing (e.g., pressure) or to create optical paths free of dielectric and protected from the harsh chemistry steps of the WLFO process. This paper describes new developments on KOZ, implemented with SU-8 photoresist as a WLFO dielectric, whose application is a novelty in the WLFO platform. The use of SU-8 and the KOZ with it, addresses some gaps of the current WLFO technology towards the integration of chips with bio-sensitive areas and sensors with low thermal budget. Due to its well-known bio-compatibility and inert behavior, SU-8 can be used as a neutral dielectric to be in direct contact to target fluids (e.g., sera, blood). Also, due to its low curing temperature, SU-8 allows a very low temperature WLFO process and thus the embedding of temperature-limited devices that have been outside the WLFO realm, for example, magneto-resistive or magnetic-spin sensor chips, which degrades its performance above 160°C. More interestingly, SU-8 exhibits a particular non-conformal behavior, which creates very smooth surfaces even over the mildly rough mold compound area of a fan-out package. Adding to this, SU-8 is readily available in the market in a wide range of thicknesses, spanning from 0.5 μm to >100 μm, and further allowing multiple spin coatings to build thick layers. Thus, SU-8 can provide smooth and deep enough channels for microfluidic flow over the chip sensing areas and, at the same time, provide the necessary layer thickness discrimination for the KOZ mechanism. Combining these features, the SU-8 layers in WLFO can play the triple role of 1) RDL dielectric insulation, 2) KOZ mechanism and 3) embedded microfluidic channels as part of the RDL. In summary, besides the unprecedented use of SU-8 in WLFO packaging, KOZ implementation on SU-8 provides a true, attainable bridge between WLFO and integrated microfluidic applications, for biosensing and biomedical applications in general. Outlooking the potentialities of such a merge, a Fan-Out package can embed several chips interconnected by RDL lines, as it currently allows, and also connected by microfluidic channel for multi-point, multi-function biosensing, constituting a true Lab-on-Package, cost-effective solution. Instead of building all sensing areas and microfluidic channels over a large silicon (Si) chip, this solution builds the feed-in, feed-out areas of the microfluidic channel over the inexpensive fan-out area, minimizing the sensing chip area, with the consequent front-end cost reduction.

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