Low Thermal Budget Crystallization of Amorphous Silicon by Nanoclusters

2009 ◽  
Vol 12 (9) ◽  
pp. H319 ◽  
Author(s):  
Il-Suk Kang ◽  
Sung-Hun Yu ◽  
Hyun-Sang Seo ◽  
Jeong-Hun Kim ◽  
Jun-Mo Yang ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Thermal Budget ◽  
Low Thermal Budget

Low-Resistivity Amorphous Silicon for Contacts Using Low-Temperature Rapid Thermal Annealing

1992 ◽  
Vol 258 ◽  
Author(s):  
Lynnita Knoch ◽  
Gordon Tam ◽  
N. David Theodore ◽  
Ron Pennell
Keyword(s):  
Low Temperature ◽  
Ion Implantation ◽  
Grain Boundaries ◽  
Amorphous Silicon ◽  
Sheet Resistance ◽  
Rapid Thermal Annealing ◽  
Thermal Budget ◽  
Temperature Rapid Thermal Annealing ◽  
Low Thermal Budget ◽  
Polycrystalline Deposition

ABSTRACTFabrication of SiGe heterojunction bipolar transistors (HBTs) requires a low thermal budget to avoid relaxation of the strained SiGe base layer. Ion implantation is one of the most widely used techniques to achieve contacts. However, due to thermal budget constraints, low temperature rapid thermal annealing (RTA) cycles to activate these implants are insufficient to anneal out all of the implant damage. Polysilicon contacts provide an alternative to ion implantation, but are typically annealed at high temperatures (>950°C) to achieve low sheet resistivity. In this study, amorphous silicon and polycrystalline silicon films were implanted with boron, arsenic, or phosphorus and RTA'd at temperatures from 800°C to 950°C and compared to single crystal silicon with identical implants and RTA cycles. The films were characterized using four-point probe, Hall measurements, TEM (transmission electron microscopy), and SIMS (secondary-ion mass-spectrometry). TEM analysis shows that the amorphous deposition produces larger grains upon RTA due to more rapid grain growth than the polycrystalline deposition. The sheet resistance for the amorphous deposited films is much lower than that of the polycrystalline deposition for all implant conditions. Activations of the implants indicate that the arsenic and phosphorus segregate to the grain boundaries, while the boron does not. The segregation is more significant for the polycrystalline films than for the amorphous films and can be explained by the grain boundary area. For contacts to the SiGe HBT, which requires a low thermal budget, an amorphous deposited silicon film is advantageous over a polycrystalline film at low annealing temperatures because it has lower sheet resistance, less segregation to the grain boundaries, and produces larger grains.

Dopant Enhanced Grain Growth During Crystallization of Amorphous Silicon Using Rapid Thermal Anealing

1990 ◽  
Vol 182 ◽  
Author(s):  
R. Kakkad ◽  
S. J. Fonash ◽  
P. R. Howell
Keyword(s):  
Ion Implantation ◽  
Amorphous Silicon ◽  
Grain Growth ◽  
Thermal Budget ◽  
Low Resistivity ◽  
Annealing Temperatures ◽  
Grain Sizes ◽  
Precursor Material ◽  
Low Thermal Budget

AbstractPECVD a-Si deposited at 250ºC on 7059 glass was used as precursor material to produce low resistivity large grain doped poly Si. The films doped in the range of 1020−1021 cm-3 with P during growth or by ion implantation wereannealed at 700ºC for times 2 to 5 minutes using RTA. A dopant enhanced grain growth was observed with grain sizes of the order of 3 μm for films of only 2000Å thickness. Resistivity as low as 6x10-4 Ω-cm and mobility as highas 34 cm2 /V-sec. were obtained using this low thermal budget process.These values are comparable to those obtained in the literature using significantly higher annealing temperatures.

Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

2010 ◽  
Vol 16 (1) ◽  
pp. 106-113 ◽  
Author(s):  
Kah-Wee Ang ◽  
Tsung-Yang Liow ◽  
Ming-Bin Yu ◽  
Qing Fang ◽  
Junfeng Song ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget ◽  
Low Thermal Budget

Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration

2018 ◽  
Author(s):  
Zhicheng Wu ◽  
Jacopo Franco ◽  
Anne Vandooren ◽  
Ben Kaczer ◽  
Philippe Roussel ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Low Thermal Budget

Implementation of Wafer Level Packaging KOZ using SU-8 as Dielectric for the Merging of WL Fan Out to Microfluidic and Biomedical Applications

2017 ◽  
Vol 2017 (1) ◽  
pp. 000569-000575 ◽  
Author(s):  
André Cardoso ◽  
Raquel Pinto ◽  
Elisabete Fernandes ◽  
Steffen Kroehnert
Keyword(s):  
Biomedical Applications ◽  
Microfluidic Channel ◽  
Cost Effective ◽  
Curing Temperature ◽  
Microfluidic Channels ◽  
Wafer Level ◽  
Thermal Budget ◽  
Chip Area ◽  
Wide Range ◽  
Low Thermal Budget

Abstract Due to its versatility for high density, heterogeneous integration, Wafer Level Fan Out (WLFO) packaging has recently seen a tremendous growth in a broad array of applications, from telecommunications and automotive, to optical and environmental sensing, while addressing the challenges of the next big wave of the Internet of Things (IoT). In this context, WLFO is continuously being challenged to include new families of MEMS/NEMS/MOEMS sensors, low thermal budget devices and biochips with microfluidics for biomedical applications. Recent developments in WLFO technology by NANIUM [1] demonstrated the implementation of a keep-out-zone (KOZ) mechanism intended to 1st) protect sensitive sensor areas during the backend processing of WLFO wafers and 2nd) create open zones on the Re-Distribution Layers (RDL). This way, the KOZ mechanism provides a physical, direct path from the embedded device to the environment. This is a necessary feature for environment sensing (e.g., pressure) or to create optical paths free of dielectric and protected from the harsh chemistry steps of the WLFO process. This paper describes new developments on KOZ, implemented with SU-8 photoresist as a WLFO dielectric, whose application is a novelty in the WLFO platform. The use of SU-8 and the KOZ with it, addresses some gaps of the current WLFO technology towards the integration of chips with bio-sensitive areas and sensors with low thermal budget. Due to its well-known bio-compatibility and inert behavior, SU-8 can be used as a neutral dielectric to be in direct contact to target fluids (e.g., sera, blood). Also, due to its low curing temperature, SU-8 allows a very low temperature WLFO process and thus the embedding of temperature-limited devices that have been outside the WLFO realm, for example, magneto-resistive or magnetic-spin sensor chips, which degrades its performance above 160°C. More interestingly, SU-8 exhibits a particular non-conformal behavior, which creates very smooth surfaces even over the mildly rough mold compound area of a fan-out package. Adding to this, SU-8 is readily available in the market in a wide range of thicknesses, spanning from 0.5 μm to >100 μm, and further allowing multiple spin coatings to build thick layers. Thus, SU-8 can provide smooth and deep enough channels for microfluidic flow over the chip sensing areas and, at the same time, provide the necessary layer thickness discrimination for the KOZ mechanism. Combining these features, the SU-8 layers in WLFO can play the triple role of 1) RDL dielectric insulation, 2) KOZ mechanism and 3) embedded microfluidic channels as part of the RDL. In summary, besides the unprecedented use of SU-8 in WLFO packaging, KOZ implementation on SU-8 provides a true, attainable bridge between WLFO and integrated microfluidic applications, for biosensing and biomedical applications in general. Outlooking the potentialities of such a merge, a Fan-Out package can embed several chips interconnected by RDL lines, as it currently allows, and also connected by microfluidic channel for multi-point, multi-function biosensing, constituting a true Lab-on-Package, cost-effective solution. Instead of building all sensing areas and microfluidic channels over a large silicon (Si) chip, this solution builds the feed-in, feed-out areas of the microfluidic channel over the inexpensive fan-out area, minimizing the sensing chip area, with the consequent front-end cost reduction.

Sign in / Sign up

Export Citation Format

Share Document