scholarly journals Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Micromachines ◽  
2020 ◽  
Vol 11 (8) ◽  
pp. 741
Author(s):  
Tung-Ying Hsieh ◽  
Ping-Yi Hsieh ◽  
Chih-Chao Yang ◽  
Chang-Hong Shen ◽  
Jia-Min Shieh ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Laser Annealing ◽  
Three Dimensional ◽  
Far Infrared ◽  
Superior Performance ◽  
Nanosecond Laser ◽  
Thermal Budget ◽  
Si Nanowire ◽  
Single Grain ◽  
Low Thermal Budget

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing

2017 ◽  
Vol 10 (2) ◽  
pp. 026502 ◽  
Author(s):  
Wen-Hsien Huang ◽  
Jia-Min Shieh ◽  
Ming-Hsuan Kao ◽  
Chang-Hong Shen ◽  
Tzu-En Huang ◽  
...  
Keyword(s):  
Laser Annealing ◽  
Pulsed Laser ◽  
Thermal Budget ◽  
Pulsed Laser Annealing ◽  
Low Thermal Budget

Monolithic 3D Integration of Single-Grain Si TFTs

2008 ◽  
Vol 1066 ◽  
Author(s):  
Mohammad Reza Tajari Mofrad ◽  
Ryoichi Ishihara ◽  
Jaber Derakhshandeh ◽  
Alessandro Baiano ◽  
Johan van der Cingel ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Three Dimensional ◽  
Bottom Layer ◽  
Switching Voltage ◽  
3D Integration ◽  
Monolithically Integrated ◽  
Interconnect Delay ◽  
Single Grain ◽  
Voltage Swing

ABSTRACTVertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. NMOS mobilities are 565 and 393 cm2/Vs and pMOS mobilities are 159 and 141 cm2/Vs, for the top and bottom layers respectively. A three-dimensional (3D) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. The inverters showed an output voltage swing of 0 to 5 V with a switching voltage of around 2 V.

Low Thermal Budget Ohmic Contact Formation by Laser Anneal

2016 ◽  
Vol 858 ◽  
pp. 565-568 ◽  
Author(s):  
Fulvio Mazzamuto ◽  
Sebastien Halty ◽  
Hideaki Tanimura ◽  
Yoshihiro Mori
Keyword(s):  
Ohmic Contact ◽  
Laser Annealing ◽  
Process Window ◽  
Nickel Deposition ◽  
Thermal Budget ◽  
Melt Annealing ◽  
Low Thermal Budget ◽  
Induced Defects ◽  
Wafer Thinning ◽  
Thinning Process

In this work, we demonstrate the possibility to achieve an ohmic contact using a low thermal budget applicable to backside processing after wafer thinning. The process window for laser annealing as a function of the thinning process is investigated. By laser melt annealing, we demonstrate the possibility for different silicide phases from pure nickel deposition on thinned 4H-SiC, formation of uniform carbon nanoclusters at the metal/SiC interface and recovery of thinning-induced defects. This has been demonstrated as a function of different thinning process and surface conditions.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Short Channel Poly-Si TFT with Single Grain Boundary by Excimer Laser Annealing on Al-masked a-Si Layer

2002 ◽  
Vol 715 ◽  
Author(s):  
Sang-Hoon Jung ◽  
Jae-Hoon Lee ◽  
Min-Koo Han
Keyword(s):  
Grain Boundary ◽  
Laser Annealing ◽  
Thin Film Transistor ◽  
High Mobility ◽  
Silicon Layer ◽  
Silicon Thin Film ◽  
Short Channel ◽  
Excimer Laser Annealing ◽  
Boundary Density ◽  
Single Grain

AbstractA short channel polycrystalline silicon thin film transistor (poly-Si TFT), which has single grain boundary in the center of channel, is reported. The reported poly-Si TFT employs lateral grain growth method through aluminum patterns, which acts as a selective beam mask and a lateral heat sink during the laser irradiation, on an amorphous silicon layer. The electrical characteristics of the proposed poly-Si TFT have been considerably improved due to grain boundary density lowered. The reported short channel poly-Si TFT with single grain boundary exhibits high mobility as 222 cm2/Vsec and large on/off current ratio exceeding 1 × 108.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

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