A New Method to Extract EOT of Ultrathin Gate Dielectric With High Leakage Current

2004 ◽  
Vol 25 (9) ◽  
pp. 655-657 ◽  
Author(s):  
Z. Luo ◽  
T.P. Ma
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
New Method ◽  
High Leakage Current

Barium Zirconate Nickelate as the Gate Dielectric for Low-Leakage Current Organic Transistors

2018 ◽  
Vol 65 (2) ◽  
pp. 680-686 ◽  
Author(s):  
Cheng-Jung Lee ◽  
Ke-Jing Lee ◽  
Yu-Chi Chang ◽  
Li-Wen Wang ◽  
Der-Wei Chou ◽  
...  
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Organic Transistors ◽  
Barium Zirconate ◽  
Low Leakage ◽  
Low Leakage Current

scholarly journals Improvement on Leakage Current Performance of Semiconductor IC Packages by Eliminating ESD Events

2018 ◽  
Vol 6 (5) ◽  
Author(s):  
Frederick Ray Gomez
Keyword(s):  
Product Quality ◽  
Leakage Current ◽  
Integrated Circuit ◽  
Six Sigma ◽  
Electrostatic Discharge ◽  
Assembly Process ◽  
Technical Paper ◽  
High Leakage Current ◽  
Better Than

The technical paper discusses the reduction of high leakage current failures of semiconductor IC (integrated circuit) packages by eliminating the ESD (electrostatic discharge) events during assembly process and ensuring the appropriate machine grounding and ESD controls.  It is imperative to reduce or ideally eliminate the leakage current failures of the device to ensure the product quality, especially as the market becomes more challenging and demanding.  After implementation of the corrective and improvement actions, high leakage current occurrence was reduced from baseline of 5784 ppm to 1567 ppm, better than the six sigma goal of 4715 ppm.

scholarly journals 102 The proposal of method reducing the leakage current in an elevator : New method of the passive filter

2009 ◽  
Vol 2008 (0) ◽  
pp. 23-26 ◽  
Author(s):  
Junji TAKEDA ◽  
Kazuo SHIMANE ◽  
Takayoshi TAKEDA ◽  
Hiroaki MATSUOKA ◽  
Hiroshi MOCHIKAWA ◽  
...  
Keyword(s):  
Leakage Current ◽  
New Method ◽  
Passive Filter

scholarly journals A System Engineering Approach Using FMEA and Bayesian Network for Risk Analysis—A Case Study

2019 ◽  
Vol 12 (1) ◽  
pp. 77 ◽  
Author(s):  
Sima Rastayesh ◽  
Sajjad Bahrebar ◽  
Frede Blaabjerg ◽  
Dao Zhou ◽  
Huai Wang ◽  
...  
Keyword(s):  
High Temperature ◽  
Risk Analysis ◽  
Leakage Current ◽  
System Engineering ◽  
Proton Exchange ◽  
Substrate Interface ◽  
Engineering Approach ◽  
Power Conditioner ◽  
High Leakage Current ◽  
Critical Components

This paper uses a system engineering approach based on the Failure Mode and Effect Analysis (FMEA) methodology to do risk analysis of the power conditioner of a Proton Exchange Membrane Fuel Cell (PEMFC). Critical components with high risk, common cause failures and effects are identified for the power conditioner system as one of the crucial parts of the PEMFCs used for backup power applications in the telecommunication industry. The results of this paper indicate that the highest risk corresponds to three failure modes including high leakage current due to the substrate interface of the metal oxide semiconductor field effect transistor (MOSFET), current and electrolytic evaporation of capacitor, and thereby short circuit, loss of gate control, and increased leakage current due to gate oxide of the MOSFET. The MOSFETs, capacitors, chokes, and transformers are critical components of the power stage, which should be carefully considered in the development of the design production and implementation stage. Finally, Bayesian networks (BNs) are used to identify the most critical failure causes in the MOSFET and capacitor as they are classified from the FMEA as key items based on their Risk Priority Numbers (RPNs). As a result of BNs analyses, high temperature and overvoltage are distinguished as the most crucial failure causes. Consequently, it is recommended for designers to pay more attention to the design of MOSFETs’ failure due to high leakage current owing to substrate interface, which is caused by high temperature. The results are emphasizing design improvement in the material in order to be more resistant from high temperature.

Low voltage stress-induced leakage current in 1.4–2.1 nm SiON and HfSiON gate dielectric layers

2005 ◽  
Vol 20 (8) ◽  
pp. 668-672 ◽  
Author(s):  
Robert O'Connor ◽  
Stephen McDonnell ◽  
Greg Hughes ◽  
Robin Degraeve ◽  
Thomas Kauerauf
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Dielectric Layers ◽  
Voltage Stress ◽  
Stress Induced Leakage Current
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