The impact of gate-oxide breakdown on SRAM stability

2002 ◽  
Vol 23 (9) ◽  
pp. 559-561 ◽  
Author(s):  
R. Rodriguez ◽  
J.H. Stathis ◽  
B.P. Linder ◽  
S. Kowalczyk ◽  
C.T. Chuang ◽  
...  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.


Author(s):  
Nobuyuki Wakai ◽  
Yuji Kobira ◽  
Hidemitsu Egawa ◽  
Masayoshi Tsutsumi

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.


2001 ◽  
Vol 664 ◽  
Author(s):  
C. Y. Wang ◽  
E. H. Lim ◽  
H. Liu ◽  
J. L. Sudijono ◽  
T. C. Ang ◽  
...  

ABSTRACTIn this paper the impact of the ESL (Etch Stop layer) nitride on the device performance especially the threshold voltage (Vt) has been studied. From SIMS analysis, it is found that different nitride gives different H concentration, [H] in the Gate oxide area, the higher [H] in the nitride film, the higher H in the Gate Oxide area and the lower the threshold voltage. It is also found that using TiSi instead of CoSi can help to stop the H from diffusing into Gate Oxide/channel area, resulting in a smaller threshold voltage drift for the device employed TiSi. Study to control the [H] in the nitride film is also carried out. In this paper, RBS, HFS and FTIR are used to analyze the composition changes of the SiN films prepared using Plasma enhanced Chemical Vapor deposition (PECVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) with different process parameters. Gas flow ratio, RF power and temperature are found to be the key factors that affect the composition and the H concentration in the film. It is found that the nearer the SiN composition to stoichiometric Si3N4, the lower the [H] in SiN film because there is no excess silicon or nitrogen to be bonded with H. However the lowest [H] in the SiN film is limited by temperature. The higher the process temperature the lower the [H] can be obtained in the SiN film and the nearer the composition to stoichiometric Si3N4.


1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain

2001 ◽  
Vol 59 (1-4) ◽  
pp. 155-160 ◽  
Author(s):  
B Kaczer ◽  
R Degraeve ◽  
A De Keersgieter ◽  
M Rasras ◽  
G Groeseneken

1997 ◽  
Vol 473 ◽  
Author(s):  
Tien-Chun Yang ◽  
Navakanta Bhat ◽  
Krishna C. Saraswat

ABSTRACTWe demonstrate that the reliability of ultrathin (< 10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on the position at the substrate for constant current gate injection (Vg-). The oxide breakdown strength (Qbd) is less for p+ poly-Si gate than for n+ poly-Si gate, but, it is independent of the substrate doping type. The degradation of oxides is closely related to the electric field across the gate oxide, which is influenced by the cathode Fermi level. P+ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field must be higher to give the same injection current density. A higher electric field gives more high energy electrons at the anode, and therefore the damage is more at the substrate interface. Different substrate types cause no effect on the oxide electric field, and as a result, they do not influence the degradation.


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