scholarly journals Exploiting Existing Copies in Register File for Soft Error Correction

2016 ◽  
Vol 15 (1) ◽  
pp. 17-20 ◽  
Author(s):  
Abdulaziz Eker ◽  
Oguz Ergin
Keyword(s):  
Error Correction ◽  
Soft Error ◽  
Register File

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

Half-select free bit-line sharing 12T SRAM with double-adjacent bits soft error correction and a reconfigurable FPGA for low-power applications

2019 ◽  
Vol 104 ◽  
pp. 10-22 ◽  
Author(s):  
Vishal Sharma ◽  
Pranshu Bisht ◽  
Abhishek Dalal ◽  
Maisagalla Gopal ◽  
Santosh Kumar Vishvakarma ◽  
...  
Keyword(s):  
Low Power ◽  
Error Correction ◽  
Soft Error

scholarly journals An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

2015 ◽  
Vol E98.C (7) ◽  
pp. 741-750
Author(s):  
Takashi IMAGAWA ◽  
Masayuki HIROMOTO ◽  
Hiroyuki OCHI ◽  
Takashi SATO
Keyword(s):  
Error Correction ◽  
Soft Error ◽  
Error Tolerance ◽  
Time Redundancy ◽  
Correction Scheme
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