Mixed error correction scheme and its design optimization for soft-error tolerant datapaths

2016 ◽  
Author(s):  
Junghoon Oh ◽  
Mineo Kaneko
Keyword(s):  
Design Optimization ◽  
Error Correction ◽  
Soft Error ◽  
Correction Scheme

scholarly journals An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs

2015 ◽  
Vol E98.C (7) ◽  
pp. 741-750
Author(s):  
Takashi IMAGAWA ◽  
Masayuki HIROMOTO ◽  
Hiroyuki OCHI ◽  
Takashi SATO
Keyword(s):  
Error Correction ◽  
Soft Error ◽  
Error Tolerance ◽  
Time Redundancy ◽  
Correction Scheme

A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

2013 ◽  
Vol 373-375 ◽  
pp. 1607-1611
Author(s):  
Hong Gang Zhou ◽  
Shou Biao Tan ◽  
Qiang Song ◽  
Chun Yu Peng
Keyword(s):  
Error Correction ◽  
Low Voltage ◽  
Cmos Technology ◽  
Soft Error ◽  
Error Correction Codes ◽  
Cell Design ◽  
Low Voltage Operation ◽  
Sram Cell ◽  
Simulation Results ◽  
Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

scholarly journals Efficient error correcting scheme for chaos shift keying signals

2019 ◽  
Vol 9 (5) ◽  
pp. 3550
Author(s):  
Hikmat N. Abdullah ◽  
Thamir R. Saeed ◽  
Asaad H. Sahar
Keyword(s):  
Error Correction ◽  
Logistic Map ◽  
Chaotic Sequence ◽  
Chaos Communication ◽  
Shortest Distance ◽  
Correction Scheme ◽  
Shift Keying ◽  
Minimum Delay ◽  
Modified Logistic Map ◽  
Chaos Shift Keying

An effective error-correction scheme based on normalized correlation for a non coherent chaos communication system with no redundancy bits is proposed in this paper. A modified logistic map is used in the proposed scheme for generating two sequences, one for every data bit value, in a manner that the initial value of the next chaotic sequence is set by the second value of the present chaotic sequence of the similar symbol. This arrangement, thus, has the creation of successive chaotic sequences with identical chaotic dynamics for error correction purpose. The detection symbol is performed prior to correction, on the basis of the suboptimal receiver which anchors on the computation of the shortest distance existing between the received sequence and the modified logistic map’s chaotic trajectory. The results of the simulation reveal noticeable Eb/No improvement by the proposed scheme over the prior to the error- correcting scheme with the improvement increasing whenever there is increase in the number of sequence N. Prior to the error-correcting scheme when N=8, a gain of 1.3 dB is accomplished in E<sub>b</sub>/N<sub>o</sub> at 10<sup>-3 </sup>bit error probability. On the basis of normalized correlation, the most efficient point in our proposed error correction scheme is the absence of any redundant bits needed with minimum delay procedure, in contrast to earlier method that was based on suboptimal method detection and correction. Such performance would render the scheme good candidate for applications requiring high rates of data transmission.

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