scholarly journals Single-Chip Multiple-Frequency ALN MEMS Filters Based on Contour-Mode Piezoelectric Resonators

2007 ◽  
Vol 16 (2) ◽  
pp. 319-328 ◽  
Author(s):  
Gianluca Piazza ◽  
Philip J. Stephanou ◽  
Albert P. Pisano
Keyword(s):  
Multiple Frequency ◽  
Single Chip ◽  
Piezoelectric Resonators ◽  
Contour Mode

Single-chip multiple-frequency VHF low-impedance micro piezoelectric resonators

2006 ◽  
Vol 27 (4) ◽  
pp. 246-248 ◽  
Author(s):  
L. Yan ◽  
Wei Pang ◽  
Eun Sok Kim ◽  
W.C. Tang
Keyword(s):  
Multiple Frequency ◽  
Single Chip ◽  
Piezoelectric Resonators

The Study and Experiment of Advance Control of Chaotic Vibration Mill with High Vibration Intensity Based on SCM (II) — The System Construction and the Controlling Methods

2012 ◽  
Vol 256-259 ◽  
pp. 2914-2917
Author(s):  
Xiao Lan Yang ◽  
Ji Feng Liu ◽  
Zeng Wen Xiao ◽  
Fang Min Xu
Keyword(s):  
System Construction ◽  
Constraint Condition ◽  
Multiple Frequency ◽  
Single Chip ◽  
Single Chip Microcomputer ◽  
Frequency Curve ◽  
Multiple Wave ◽  
Vibration Intensity ◽  
On Line ◽  
Vibration Mill

A intelligent variable frequency amplitude reduction advance control system whose single-chip-microcomputer act as the core controller is built, and the vibration frequency curve with multiple wave variable sine increase and decrease periodic cycle is applied as the input frequency curve, which made the vibration mill have multiple frequency and amplitude. The control methods are studied, and the operation program is debugged. By using the sensor signal amplification, A/D conversion, on-line monitoring, data mining, and the forecast of the extreme value point of the vibration intensity and its distribution, and then by conducting the judgment, detection, correction and real-time feedback of constraint condition to achieve advance control of vibration intensity over-limit and over-time.

Data Acquisition of BZD Low Burst and Intelligent Protection in the Mine

2012 ◽  
Vol 529 ◽  
pp. 331-334
Author(s):  
Chun Guang Li ◽  
Jun Mei Geng
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Low Cost ◽  
Multiple Frequency ◽  
Single Chip ◽  
Frequency Signal ◽  
High Speed Data Acquisition ◽  
High Speed Data ◽  
The Common ◽  
Rapid Processing

To describe the Underground low-pressure explosion-proof switch which has to require rapid processing of multiple frequency signal, the paper analyzes the specific signal and the common algorithms, according to the characteristics of the explosion-proof switch protection device to provide the high-precision, low-cost and high-speed data acquisition methods based on the single chip controller, which is also applied the BZD low burst intelligent protection.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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