Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space

2016 ◽  
Author(s):  
Dylan Stow ◽  
Itir Akgun ◽  
Russell Barnes ◽  
Peng Gu ◽  
Yuan Xie
Keyword(s):  
Thermal Analysis ◽  
Circuit Design ◽  
Integrated Circuit ◽  
High Performance ◽  
Design Space ◽  
Integrated Circuit Design

scholarly journals CHIP: Clustering Hotspots in Layout Using Integer Programming

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Rohit Reddy Takkala ◽  
Chris Chu
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Design Space Exploration ◽  
Design Space ◽  
Triangle Inequality ◽  
Clustering Algorithms ◽  
Test Cases ◽  
Integrated Circuit Design ◽  
Yield Optimization ◽  
Clustering Problems

Clustering algorithms have been explored in recent years to solve hotspot clustering problems in integrated circuit design. With various applications in design for manufacturability flow such as hotspot library generation, systematic yield optimization, and design space exploration, generating good quality clusters along with their representative clips is of utmost importance. With several generic clustering algorithms at our disposal, hotspots can be clustered based on the distance metric defined while satisfying some tolerance conditions. However, the clusters generated from generic clustering algorithms need not achieve optimal results. In this paper, we introduce two optimal integer linear programming formulations based on triangle inequality to solve the problem of minimizing cluster count while satisfying given constraints. Apart from minimizing cluster count, we generate representative clips that best represent the clusters formed. We achieve a better cluster count for both formulations in most test cases as compared to the results published in the literature in the ICCAD 2016 contest benchmarks as well as the reference results reported in the ICCAD 2016 contest website.

A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

2007 ◽  
Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Circuit Design ◽  
Process Design ◽  
Integrated Circuit ◽  
Photon Emission ◽  
Integrated Circuit Design ◽  
Nano Scale ◽  
Leakage Path ◽  
Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

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