Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications

While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

A Typical MOSFET Modeling Procedure for RF Analog Circuit Design

This paper presents a theoretical yet practical device targeting method to extract typical model parameters of MOSFET devices on wafer for RF analog integrated circuit design. This method employs skewing algorithms with model parameters of existing typical device which are selected by using inter-lot process electrical test parameters. Although this technique can be applied for both n-channel and p-channel MOSFETs, only n-channel devices could be prepared for our experiments in this research. To demonstrate the plausibility of this method, a cascode amplifier is designed to simulate frequency characteristic of S21 with this method.