2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial
Latest Publications

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Published By IEEE

9781424418107

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Analysing the effect of process variation to reduce parametric yield loss

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567272 ◽

2008 ◽

Cited By ~ 6

Author(s):

H. Ramakrishnan ◽

S. Shedabale ◽

G. Russell ◽

A. Yakovlev

Keyword(s):

Yield Loss ◽

Process Variation ◽

Parametric Yield

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Traces of errors due to single ion in floating gate memories

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567285 ◽

2008 ◽

Cited By ~ 1

Author(s):

G. Cellere ◽

A. Paccagnella ◽

A. Visconti ◽

M. Bonanomi ◽

R. Harboe-Sorensen ◽

...

Keyword(s):

Floating Gate

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Energy delay optimization methodology for current-mode signaling for on-chip interconnects

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567266 ◽

2008 ◽

Cited By ~ 1

Author(s):

Astria Nur Irfansyah ◽

Torsten Lehmann ◽

Saeid Nooshabadi

Keyword(s):

Current Mode ◽

Delay Optimization ◽

Optimization Methodology ◽

On Chip

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SOI chip design and charging damage

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567252 ◽

2008 ◽

Cited By ~ 1

Author(s):

Terence B. Hook

Keyword(s):

Chip Design

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Use of the p-floating shielding layer for improving electric field concentration of the recessed gate

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567235 ◽

2008 ◽

Author(s):

Sang Jun Hwang ◽

Seung Woo Yu ◽

Jae In Lee ◽

Ey-Goo Kang ◽

Man Young Sung

Keyword(s):

Electric Field ◽

Recessed Gate

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Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567239 ◽

2008 ◽

Author(s):

Junho Moon ◽

Sanghoon Hwang ◽

Daeyoon Kim ◽

Heewon Kang ◽

Seungjin Yeo ◽

...

Keyword(s):

Adaptive Control ◽

Current Steering ◽

Control Switch ◽

Layout Technique ◽

A Current

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An integrated class D audio amplifier based on sliding mode control

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567259 ◽

2008 ◽

Cited By ~ 6

Author(s):

Gael Pillonnet ◽

Remy Cellier ◽

Nacer Abouchi ◽

Monique Chiollaz

Keyword(s):

Sliding Mode Control ◽

Sliding Mode ◽

Mode Control ◽

Audio Amplifier ◽

Class D

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Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567273 ◽

2008 ◽

Cited By ~ 1

Author(s):

Kiyoo Itoh

Keyword(s):

Low Voltage ◽

Personal View ◽

Nano Scale

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Dynamic measurement of critical-path timing

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567288 ◽

2008 ◽

Cited By ~ 21

Author(s):

Alan J. Drake ◽

Robert M. Senger ◽

Harmander Singh ◽

Gary D. Carpenter ◽

Norman K. James

Keyword(s):

Critical Path ◽

Dynamic Measurement

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Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial ◽

10.1109/icicdt.2008.4567260 ◽

2008 ◽

Cited By ~ 6

Author(s):

Jose-Angel Diaz-Madrid ◽

Harald Neubauer ◽

Gines Domenech-Asensi ◽

Ramon Ruiz

Keyword(s):

Comparative Analysis ◽

Operational Amplifier ◽

Pipelined Adc

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2008 IEEE International Conference on Integrated Circuit Design and Technology and TutorialLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Analysing the effect of process variation to reduce parametric yield loss

Traces of errors due to single ion in floating gate memories

Energy delay optimization methodology for current-mode signaling for on-chip interconnects

SOI chip design and charging damage

Use of the p-floating shielding layer for improving electric field concentration of the recessed gate

Design of a current steering CMOS D/A converter with an adaptive control switch and a novel layout technique

An integrated class D audio amplifier based on sliding mode control

Low-voltage limitations and challenges of nano-scale CMOS LSIs - A personal view of memory designer -

Dynamic measurement of critical-path timing

Comparative analysis of two operational amplifier topologies for a 40MS/s 12-bit pipelined ADC in 0.35μm CMOS

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial
Latest Publications