Hardware optimizations for crypto implementations (Invited paper)

2016 ◽  
Author(s):  
M Mohamed Asan Basiri ◽  
Sandeep K. Shukla
Keyword(s):  
Hardware Optimizations

FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG

2016 ◽  
pp. 78-90 ◽  
Author(s):  
Colm Kelly ◽  
Fahad Manzoor Siddiqui ◽  
Burak Bardak ◽  
Yun Wu ◽  
Roger Woods ◽  
...  
Keyword(s):  
Soft Core ◽  
Hardware Optimizations

scholarly journals Hardware optimizations of stream cipher rabbit

2011 ◽  
Vol 50 (1) ◽  
pp. 87-101
Author(s):  
Jozef Tomecek
Keyword(s):  
Stream Cipher ◽  
Stream Ciphers ◽  
Optimization Techniques ◽  
Cryptographic Primitives ◽  
Trade Offs ◽  
Algorithm Comparison ◽  
Form Part ◽  
Hardware Optimizations ◽  
Hardware Performance

ABSTRACT Stream ciphers form part of cryptographic primitives focused on privacy. Synchronous, symmetric and software-oriented stream cipher Rabbit is member of final portfolio of European Union's eStream project. Although it was designed to perform well in software, employed operations seem to compute effi­ciently in hardware. 128-bit security, with no known security weaknesses is claimed by Rabbit's designers. Since hardware performance of Rabbit was only estimated in the proposal of algorithm, comparison of direct and optimized FPGA im­plementations of Rabbit stream cipher is presented, identifying algorithm bot­tlenecks, discussing optimization techniques applied to algorithm computations, along with key area/time trade-offs.

Improvement of Modal Mass Analysis with Analyzer Hardware Optimizations and Mathematically Enhanced Response Time

2004 ◽  
Author(s):  
Ichiro Asano ◽  
Hiroshi Nakamura ◽  
Masaru Miyai ◽  
Masayuki Adachi ◽  
Kenzo Hosoi
Keyword(s):  
Response Time ◽  
Mass Analysis ◽  
Modal Mass ◽  
Hardware Optimizations

scholarly journals Investigating Memory System Energy Behavior Using Software and Hardware Optimizations

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 151-165 ◽  
Author(s):  
G. Esakkimuthu ◽  
H. S. Kim ◽  
M. Kandemir ◽  
N. Vijaykrishnan ◽  
M. J. Irwin
Keyword(s):  
Compiler Optimization ◽  
Memory System ◽  
Quantitative Comparison ◽  
Optimization Techniques ◽  
Compiler Optimizations ◽  
Cache Optimization ◽  
Energy Behavior ◽  
Software And Hardware ◽  
System Energy ◽  
Hardware Optimizations

Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms and three widely used compiler optimization techniques used to reduce the memory system energy. Our presentation is in two parts. First, we focus on a set of memory-intensive benchmark codes and investigate their memory system energy behavior due to data accesses under hardware and compiler optimizations. Then, using four motion estimation codes, we look at the influence of compiler optimizations on the memory system energy considering the overall impact of instruction and data accesses.

scholarly journals Algorithm, software, and hardware optimizations for Delaunay mesh generation on simultaneous multithreaded architectures

2009 ◽  
Vol 69 (7) ◽  
pp. 601-612 ◽  
Author(s):  
Christos D. Antonopoulos ◽  
Filip Blagojevic ◽  
Andrey N. Chernikov ◽  
Nikos P. Chrisochoides ◽  
Dimitrios S. Nikolopoulos
Keyword(s):  
Mesh Generation ◽  
Multithreaded Architectures ◽  
Software And Hardware ◽  
Delaunay Mesh ◽  
Hardware Optimizations

Hardware Optimizations and Analysis for the WG-16 Cipher with Tower Field Arithmetic

2019 ◽  
Vol 68 (1) ◽  
pp. 67-82
Author(s):  
Nusa Zidaric ◽  
Mark Aagaard ◽  
Guang Gong
Keyword(s):  
Hardware Optimizations
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