Derating based hardware optimizations in soft error tolerant designs

2012 ◽  
Author(s):  
V Prasanth ◽  
Virendra Singh ◽  
Rubin Parekhji
Keyword(s):  
Soft Error ◽  
Hardware Optimizations

scholarly journals Evaluating the soft error sensitivity of a GPU-based SoC for matrix multiplication

2020 ◽  
Vol 114 ◽  
pp. 113856
Author(s):  
Germán León ◽  
José M. Badía ◽  
Jose A. Belloch ◽  
Almudena Lindoso ◽  
Luis Entrena
Keyword(s):  
Matrix Multiplication ◽  
Soft Error ◽  
Error Sensitivity

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

BTI and Soft-Error Tolerant Voltage Bootstrapped Schmitt Trigger Circuit

2021 ◽  
Vol 21 (1) ◽  
pp. 153-155
Author(s):  
Neha Gupta ◽  
Ambika Prasad Shah ◽  
Santosh Kumar Vishvakarma
Keyword(s):  
Schmitt Trigger ◽  
Soft Error ◽  
Trigger Circuit ◽  
Schmitt Trigger Circuit
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