Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.993042 ◽

2003 ◽

Cited By ~ 1

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.992224 ◽

2005 ◽

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

Download Full-text

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.803938 ◽

2002 ◽

Vol 37 (11) ◽

pp. 1383-1395 ◽

Cited By ~ 51

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1145/513918.514021 ◽

2002 ◽

Cited By ~ 2

Author(s):

Mustafa Badaroglu ◽

Kris Tiri ◽

StÉphane Donnay ◽

Piet Wambacq ◽

Hugo De Man ◽

...

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Tree ◽

Tree Optimization ◽

Supply Current ◽

Current Transients

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GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) ◽

10.1109/async.2016.15 ◽

2016 ◽

Cited By ~ 1

Author(s):

Milan Babic ◽

Steffen Zeidler ◽

Milo Krstic

Keyword(s):

Integrated Circuits ◽

Noise Reduction ◽

Substrate Noise ◽

Mixed Signal

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Substrate noise reduction using active guard band filters in mixed-signal integrated circuits

Digest of Technical Papers., Symposium on VLSI Circuits. ◽

10.1109/vlsic.1995.520675 ◽

2002 ◽

Cited By ~ 8

Author(s):

K. Makie-Fukuda ◽

S. Maeda ◽

T. Tsukada ◽

T. Matsuura

Keyword(s):

Integrated Circuits ◽

Noise Reduction ◽

Substrate Noise ◽

Mixed Signal ◽

Guard Band

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The behavior of digital circuits under substrate noise in a mixed-signal smart-power environment

11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312) ◽

10.1109/ispsd.1999.764111 ◽

2003 ◽

Cited By ~ 6

Author(s):

R.M. Secareanu ◽

I.S. Kourtev ◽

J. Becerra ◽

T.E. Watrobski ◽

C. Morton ◽

...

Keyword(s):

Digital Circuits ◽

Substrate Noise ◽

Smart Power ◽

Mixed Signal

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Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2006.879065 ◽

2006 ◽

Vol 53 (8) ◽

pp. 1803-1815 ◽

Cited By ~ 11

Author(s):

M.A. Mendez ◽

D. Mateo ◽

A. Rubio ◽

J.L. Gonzalez

Keyword(s):

Experimental Verification ◽

Noise Spectrum ◽

Substrate Noise ◽

Mixed Signal

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Physical design guides for substrate noise reduction in CMOS digital circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/4.910494 ◽

2001 ◽

Vol 36 (3) ◽

pp. 539-549 ◽

Cited By ~ 56

Author(s):

M. Nagata ◽

J. Nagai ◽

K. Hijikata ◽

T. Morie ◽

A. Iwata

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Physical Design ◽

Substrate Noise

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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1109/dac.2002.1012658 ◽

2002 ◽

Cited By ~ 10

Author(s):

M. Badaroglu ◽

K. Tiri ◽

S. Donnay ◽

P. Wambacq ◽

I. Verbauwhede ◽

...

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Tree ◽

Tree Optimization ◽

Supply Current ◽

Current Transients

Download Full-text

Vertical Noise Reduction in 3D Mixed-Signal Integrated Circuits with Graphene Nanoribbon and Carbon Nanotube Interconnects

IEEE Transactions on Components Packaging and Manufacturing Technology ◽

10.1109/tcpmt.2020.3045877 ◽

2020 ◽

pp. 1-1

Author(s):

Soheila Gharavi Hamedani ◽

Mohammad Hossein Moaiyeri ◽

Masoud Meghdadi ◽

Maryam Rezaei Khezeli

Keyword(s):

Carbon Nanotube ◽

Integrated Circuits ◽

Noise Reduction ◽

Graphene Nanoribbon ◽

Mixed Signal

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