Physical design guides for substrate noise reduction in CMOS digital circuits

M. Nagata; J. Nagai; K. Hijikata; T. Morie; A. Iwata

doi:10.1109/4.910494

Physical design guides for substrate noise reduction in CMOS digital circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/4.910494 ◽

2001 ◽

Vol 36 (3) ◽

pp. 539-549 ◽

Cited By ~ 56

Author(s):

M. Nagata ◽

J. Nagai ◽

K. Hijikata ◽

T. Morie ◽

A. Iwata

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Physical Design ◽

Substrate Noise

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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1145/513918.514021 ◽

2002 ◽

Cited By ~ 2

Author(s):

Mustafa Badaroglu ◽

Kris Tiri ◽

StÉphane Donnay ◽

Piet Wambacq ◽

Hugo De Man ◽

...

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Tree ◽

Tree Optimization ◽

Supply Current ◽

Current Transients

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Quantitative characterization of substrate noise for physical design guides in digital circuits

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) ◽

10.1109/cicc.2000.852626 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Nagata ◽

J. Nagai ◽

T. Morie ◽

A. Iwata

Keyword(s):

Digital Circuits ◽

Physical Design ◽

Substrate Noise ◽

Quantitative Characterization

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.992224 ◽

2005 ◽

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.803938 ◽

2002 ◽

Vol 37 (11) ◽

pp. 1383-1395 ◽

Cited By ~ 51

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

Download Full-text

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.993042 ◽

2003 ◽

Cited By ~ 1

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

Download Full-text

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1109/dac.2002.1012658 ◽

2002 ◽

Cited By ~ 10

Author(s):

M. Badaroglu ◽

K. Tiri ◽

S. Donnay ◽

P. Wambacq ◽

I. Verbauwhede ◽

...

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Tree ◽

Tree Optimization ◽

Supply Current ◽

Current Transients

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GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits

2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) ◽

10.1109/async.2016.15 ◽

2016 ◽

Cited By ~ 1

Author(s):

Milan Babic ◽

Steffen Zeidler ◽

Milo Krstic

Keyword(s):

Integrated Circuits ◽

Noise Reduction ◽

Substrate Noise ◽

Mixed Signal

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Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew

10.7567/ssdm.2013.ps-5-5 ◽

2013 ◽

Author(s):

S. Shimazaki ◽

S. Taga ◽

T. Makita ◽

N. Azuma ◽

N. Miura ◽

...

Keyword(s):

High Frequency ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Skew

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3-D Transient Analysis of TSV-Induced Substrate Noise: Improved Noise Reduction in 3-D-ICs With Incorporation of Guarding Structures

IEEE Electron Device Letters ◽

10.1109/led.2014.2318301 ◽

2014 ◽

Vol 35 (6) ◽

pp. 660-662 ◽

Cited By ~ 15

Author(s):

Leo Jyun-Hong Lin ◽

Yih-Peng Chiou

Keyword(s):

Noise Reduction ◽

Transient Analysis ◽

Substrate Noise

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Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) ◽

10.1109/vlsic.2001.934226 ◽

2002 ◽

Cited By ~ 9

Author(s):

M. Nagata ◽

T. Ohmoto ◽

Y. Hlurasaka ◽

T. Morie ◽

A. Iwata

Keyword(s):

Power Supply ◽

Large Scale ◽

Digital Circuits ◽

Noise Generation ◽

Substrate Noise ◽

Parasitic Components

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