Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1109/dac.2002.1012658 ◽

2002 ◽

Cited By ~ 10

Author(s):

M. Badaroglu ◽

K. Tiri ◽

S. Donnay ◽

P. Wambacq ◽

I. Verbauwhede ◽

...

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Tree ◽

Tree Optimization ◽

Supply Current ◽

Current Transients

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Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) ◽

10.1145/513918.514021 ◽

2002 ◽

Cited By ~ 2

Author(s):

Mustafa Badaroglu ◽

Kris Tiri ◽

StÉphane Donnay ◽

Piet Wambacq ◽

Hugo De Man ◽

...

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Substrate Noise ◽

Clock Tree ◽

Tree Optimization ◽

Supply Current ◽

Current Transients

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Physical design guides for substrate noise reduction in CMOS digital circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/4.910494 ◽

2001 ◽

Vol 36 (3) ◽

pp. 539-549 ◽

Cited By ~ 56

Author(s):

M. Nagata ◽

J. Nagai ◽

K. Hijikata ◽

T. Morie ◽

A. Iwata

Keyword(s):

Noise Reduction ◽

Digital Circuits ◽

Physical Design ◽

Substrate Noise

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.992224 ◽

2005 ◽

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2002.803938 ◽

2002 ◽

Vol 37 (11) ◽

pp. 1383-1395 ◽

Cited By ~ 51

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

Download Full-text

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ◽

10.1109/isscc.2002.993042 ◽

2003 ◽

Cited By ~ 1

Author(s):

M. Badaroglu ◽

M. van Heijningen ◽

V. Gravot ◽

J. Compiet ◽

S. Donnay ◽

...

Keyword(s):

Noise Reduction ◽

Experimental Verification ◽

Digital Circuits ◽

Substrate Noise ◽

Mixed Signal

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Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.855952 ◽

2006 ◽

Vol 25 (6) ◽

pp. 1146-1154 ◽

Cited By ~ 10

Author(s):

M. Badaroglu ◽

K. Tiri ◽

G. Van der Plas ◽

P. Wambacq ◽

I. Verbauwhede ◽

...

Keyword(s):

Noise Reduction ◽

Substrate Noise ◽

Clock Skew ◽

Supply Current ◽

Optimization Methodology

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Post optimization of a clock tree for power supply noise reduction

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel ◽

10.1109/eeei.2012.6377136 ◽

2012 ◽

Author(s):

Yakov Kaplan ◽

Shmuel Wimer

Keyword(s):

Noise Reduction ◽

Power Supply ◽

Power Supply Noise ◽

Clock Tree ◽

Supply Noise

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SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty

Integration ◽

10.1016/j.vlsi.2012.04.004 ◽

2013 ◽

Vol 46 (1) ◽

pp. 22-32 ◽

Cited By ~ 5

Author(s):

Sina Basir-Kazeruni ◽

Hao Yu ◽

Fang Gong ◽

Yu Hu ◽

Chunchen Liu ◽

...

Keyword(s):

Stochastic Perturbation ◽

Clock Tree ◽

Tree Optimization

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Clock Tree Optimization of FPGA Semi-Custom Memory with SEU FlipFlops

2020 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) ◽

10.1109/iemtronics51293.2020.9216346 ◽

2020 ◽

Author(s):

Sourabh Aditya Swarnkar ◽

Kumar Rahul ◽

Mohammad Anees ◽

Santosh Yachareni

Keyword(s):

Clock Tree ◽

Tree Optimization

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OCV-aware top-level clock tree optimization

Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14 ◽

10.1145/2591513.2591541 ◽

2014 ◽

Cited By ~ 10

Author(s):

Tuck-Boon Chan ◽

Kwangsoo Han ◽

Andrew B. Khang ◽

Jae-Gon Lee ◽

Siddhartha Nath

Keyword(s):

Clock Tree ◽

Tree Optimization

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