On-chip inductance modeling of VLSI interconnects

2002 ◽  
Author(s):  
Xiaoning Qi ◽  
B. Kleveland ◽  
Zhiping Yu ◽  
S. Wong ◽  
R. Dutton ◽  
...  
Keyword(s):  
Vlsi Interconnects ◽  
On Chip

Delay and Crosstalk Aware Analysis for High Speed On-Chip Global RLC VLSI Interconnects

2021 ◽  
pp. 791-807
Author(s):  
Apoorva Gupta ◽  
Vikas Maheshwari ◽  
Somashekhar Malipatil ◽  
Rajib Kar
Keyword(s):  
High Speed ◽  
Vlsi Interconnects ◽  
On Chip

scholarly journals Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

2021 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Narendra Kumar Garg ◽  
Vivek Singh Kushwah ◽  
Manisha Pattanaik
Keyword(s):  
Digital Circuits ◽  
Leakage Power ◽  
Performance Parameters ◽  
New Techniques ◽  
Vlsi Interconnects ◽  
Digital Electronics ◽  
Spice Model ◽  
On Chip ◽  
Carbon Nano Tube ◽  
The Impact

Abstract With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

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