Comparative Analysis of On-Chip Optical and Copper VLSI Interconnects for Deep Sub-Micron Technology Nodes

2018 ◽  
Vol 13 (2) ◽  
pp. 267-274
Author(s):  
Karmjit Singh Sandha ◽  
Mahesh Kumar
Keyword(s):  
Comparative Analysis ◽  
Vlsi Interconnects ◽  
On Chip ◽  
Technology Nodes

On-chip inductance modeling of VLSI interconnects

2002 ◽  
Author(s):  
Xiaoning Qi ◽  
B. Kleveland ◽  
Zhiping Yu ◽  
S. Wong ◽  
R. Dutton ◽  
...  
Keyword(s):  
Vlsi Interconnects ◽  
On Chip

CNT as Interconnects

2020 ◽  
pp. 130-159
Author(s):  
Karmjit Singh Sandha
Keyword(s):  
Comparative Analysis ◽  
Equivalent Circuit ◽  
Integrated Circuit ◽  
Equivalent Circuit Model ◽  
Global Level ◽  
Electrical Equivalent Circuit ◽  
Swcnt Bundle ◽  
Impedance Parameters ◽  
Power Delay Product ◽  
Technology Nodes

The chapter will start with brief introduction to the interconnects and its importance in an integrated circuit at deep sub-micron technology nodes. The brief discussion about the concept of scaling, interconnects models, and material in use are presented. The limitations of conventional materials at scaled down technology nodes will be discussed next. The focus of the chapter is to present the electrical equivalent circuit model to estimate the impedance parameters of SWCNT bundle and MWCNT bundle as interconnects at different nano-scaled technology nodes for global level interconnect length. Using ESC model of SWCNT, MWCNT, and copper, the performance comparative analysis for delay and power delay product (PDP) will be presented for different interconnect lengths at nano-scaled technology nodes. Finally, the chapter summary and conclusion will be written at the end of the chapter.

Comparative analysis of network‐on‐chip simulation tools

2017 ◽  
Vol 12 (1) ◽  
pp. 30-38 ◽  
Author(s):  
Sarzamin Khan ◽  
Sheraz Anjum ◽  
Usman Ali Gulzari ◽  
Frank Sill Torres
Keyword(s):  
Comparative Analysis ◽  
Network On Chip ◽  
Simulation Tools ◽  
On Chip

Buffer for High Performance in CNT Based VLSI Interconnects

2018 ◽  
Vol 24 (8) ◽  
pp. 5975-5981
Author(s):  
A Karthikeyan ◽  
P. S Mallick
Keyword(s):  
Integrated Circuits ◽  
Packing Density ◽  
Power Dissipation ◽  
High Performance ◽  
Critical Path ◽  
Vlsi Interconnects ◽  
Performance Constraints ◽  
Interconnect Delay ◽  
Interconnect Optimization ◽  
Technology Nodes

Integrated circuits (IC’s) are sized for higher performance and packing density. Interconnects are major components to carry signals between transistors. Interconnect delay increases due to increase in length of interconnect. Optimization of interconnects is more essential to improve the performance of integrated circuits. Repeater insertion is an important technique used in optimizing the performance of interconnects in integrated circuits. Repeaters have to be designed to satisfy the performance constraints. In this paper we have designed a new repeater using transistors and analyzed the performance at various bias levels. The Repeater design was implemented at various technology nodes using PTM models and Bulk CMOS. Delay and power dissipation are analyzed for various voltage levels and load levels using Spice simulations. The results show that the proposed repeater has lesser delay compared to the conventional repeater with an increase of power dissipation and they are more suitable for Critical path in VLSI interconnects. They can be applicable for CNT based VLSI interconnects.

On-Chip Interconnect Conductor Materials for End-of-Roadmap Technology Nodes

2018 ◽  
Vol 17 (1) ◽  
pp. 4-10 ◽  
Author(s):  
Anshul A. Vyas ◽  
Changjian Zhou ◽  
Cary Y. Yang
Keyword(s):  
On Chip ◽  
Technology Nodes
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