Crosstalk noise and delay analysis for high speed on-chip global RLC VLSI interconnects with mutual inductance using 90nm process technology

2015 ◽  
Author(s):  
Apoorva Gupta ◽  
Vikas Maheshwari ◽  
Shalini Sharma ◽  
Rajib Kar
Keyword(s):  
High Speed ◽  
Mutual Inductance ◽  
Delay Analysis ◽  
Crosstalk Noise ◽  
Process Technology ◽  
Vlsi Interconnects ◽  
On Chip

Delay and Crosstalk Aware Analysis for High Speed On-Chip Global RLC VLSI Interconnects

2021 ◽  
pp. 791-807
Author(s):  
Apoorva Gupta ◽  
Vikas Maheshwari ◽  
Somashekhar Malipatil ◽  
Rajib Kar
Keyword(s):  
High Speed ◽  
Vlsi Interconnects ◽  
On Chip

scholarly journals Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic

2019 ◽  
Vol 8 (2) ◽  
pp. 101-106
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Vlsi Design ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Two Phase ◽  
Adiabatic Logic ◽  
On Chip

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.

scholarly journals Delay Approximation Model for Prime Speed Interconnects in Current Mode

2019 ◽  
Vol 8 (9) ◽  
pp. 3090-3093
Keyword(s):  
Time Delay ◽  
Transfer Function ◽  
High Speed ◽  
Current Mode ◽  
Approximation Model ◽  
Finite Difference Equation ◽  
Vlsi Interconnects ◽  
Interconnect Delay ◽  
Coupling Capacitance ◽  
On Chip

There is enormous demand for high speed VLSI networks in present days. The coupling capacitance and interconnect delay play a major role in judging the behavior of on chip interconnects. There is an on chip inductance effect as we switch to low technology that leads to delay in interconnecting. In this paper we are attempting to apply second order transfer function designed with finite difference equation and transform Laplace at the ends of the source and load termination. Analysis shows that the current signaling mode in VLSI interconnects provide better time delay than the voltage mode

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

Formal Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip with WDM

2016 ◽  
Vol 34 (15) ◽  
pp. 3550-3562 ◽  
Author(s):  
Yiyuan Xie ◽  
Tingting Song ◽  
Zhendong Zhang ◽  
Chao He ◽  
Jiachao Li ◽  
...  
Keyword(s):  
Optical Networks ◽  
Formal Analysis ◽  
Crosstalk Noise ◽  
Networks On Chip ◽  
On Chip
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