Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes

2012 ◽  
Author(s):  
Yunlong Zhang ◽  
Qiang Tong ◽  
Li Li ◽  
Wei Wang ◽  
Ken Choi ◽  
...  
Keyword(s):  
Low Power ◽  
Register Transfer Level ◽  
Tool Design ◽  
Clock Gating ◽  
Register Transfer ◽  
Cad Tool

Improved Baugh Wooley Multiplier Using Cadence Register Transfer Level Logic for Power Consumption

2017 ◽  
Vol 14 (1) ◽  
pp. 277-283
Author(s):  
V Rajmohan ◽  
O. Uma Maheswari
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Register Transfer Level ◽  
Low Power Consumption ◽  
Power Efficient ◽  
Practical Applications ◽  
Efficient Process ◽  
Array Multiplier ◽  
Register Transfer

In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster than a conventional Baugh-Wooley multiplier. The Improved Baugh-Wooley multiplier consumes the power of 09.02 mW and area of 52426 μm2.

scholarly journals Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 73
Author(s):  
Francesco Ratto ◽  
Tiziana Fanni ◽  
Luigi Raffo ◽  
Carlo Sau
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Systems Design ◽  
Hardware Acceleration ◽  
High Level Synthesis ◽  
Clock Gating ◽  
Technology Application ◽  
Positive Effects ◽  
High Level ◽  
Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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