Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique

2007 ◽  
Vol 56 (2) ◽  
pp. 243-252 ◽  
Author(s):  
Han Liang ◽  
Piyush Mishra ◽  
Kaijie Wu
Keyword(s):  
Low Power ◽  
Error Correction ◽  
Register Transfer Level ◽  
On Demand ◽  
Correction Technique ◽  
Register Transfer

Improved Baugh Wooley Multiplier Using Cadence Register Transfer Level Logic for Power Consumption

2017 ◽  
Vol 14 (1) ◽  
pp. 277-283
Author(s):  
V Rajmohan ◽  
O. Uma Maheswari
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Register Transfer Level ◽  
Low Power Consumption ◽  
Power Efficient ◽  
Practical Applications ◽  
Efficient Process ◽  
Array Multiplier ◽  
Register Transfer

In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster than a conventional Baugh-Wooley multiplier. The Improved Baugh-Wooley multiplier consumes the power of 09.02 mW and area of 52426 μm2.

scholarly journals BCH Encoder and Decoder for Emerging Memories

2021 ◽  
Vol 2 (4) ◽  
pp. 220-227
Author(s):  
Rohith R ◽  
Saji A J
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Correction ◽  
High Performance ◽  
Error Correcting Code ◽  
Correction Technique ◽  
High Performance Application ◽  
Xilinx Fpga ◽  
Decoding Efficiency ◽  
Specific Error

In this paper, an encoder and decoder system is proposed using Bose-Chaudhuri-Hocquenghem (BCH) double-error-correcting and triple-error detecting (DEC-TED) with emerging memories of low power and high decoding efficiency. An adaptive error correction technique and an invalid transition inhibition technique is enforced to the decoder. This is to improve the decoding efficiency and reduce the power consumption and delay. The adaptive error correction gives high decoding efficiency and invalid transition technique reduce the power consumption issue in conventional BCH decoders. The DEC-TED BCH decoder combines these two techniques by using a specific Error Correcting Code Clock and Flip Flops. This technique provides an error correcting encoder and decoder solution for low power and high-performance application using emerging memories. The design simulated in Xilinx FPGA using ISE Design Suite 14.5.

A Low Power SAR ADC with Digital Error Correction Technique for Wearable and Implantable ECG Devices

2021 ◽  
Vol 11 ◽  
Author(s):  
Posani Vijaya Lakshmi ◽  
Sarada Musala ◽  
Avireni Srinivasulu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Correction ◽  
Logic Gate ◽  
Process Variations ◽  
Sar Adc ◽  
Dynamic Comparator ◽  
Correction Technique ◽  
Dynamic Comparators ◽  
Low Offset

Aims: To propose an 8-bit differential input low power successive approximation register (SAR) ADC with digital error correction technique for sensing bio-potential signals in wearable and implantable devices. Background: As Dynamic comparators have the advantages of full swing output, low power consumption, high speed, and high impedance at the input, they are preferably used in energy efficient SAR ADC’s. But since dynamic comparator is the most frequently used block in SAR ADC, research is ongoing to furthermore reduce its µW power. Also, as offset voltage of comparator affects the linearity of ADC, it must be minimized. Linearity can further be improved by calibrating the output of ADC and extensive survey on the calibration methods prove that addition only digital error correction method is efficient in terms of power. Objective: To design a low power and low offset dynamic comparator intended for SAR ADC to achieve highly linear digital output. In addition to this, to implement a power efficient digital error correction technique for the output of SAR ADC to overcome the non-idealities due to process variations. Method: As power consumption is proportional to the number of transistors, proposed comparator is a design obtaining same output as the existing dynamic comparators with reduced transistor count. The proposed comparator along with low power full swing three input XOR logic gate is implemented in SAR ADC with digital error correction technique in cadence 45 nm technology files and its performance parameters are simulated. Result: The layout of the proposed dynamic comparator occupies an area of 3 µm2. The simulation results of this comparator with a load of 1 pF show that it has a total offset of 11.2 mV, delay of 0.9 ns and power consumption of 24 nW. It also achieves a gain of 49.5 i.e 33.86 dB. The 8-bit ADC along with digital error correction technique operating at 143-kS/s and under 0.6 V supply voltage simulated in 45nm technology consumes only 0.12 µW power. The DNL and INL error obtained are +0.22/-0.2 LSB and -0.28 LSB respectively. SNR limited by noise is 48.25 dB, SFDR is 48.64 dB and ENOB achieved is 7.72. Conclusion: To satisfy the requirement of the wearable and implantable devices a low power SAR ADC with good linearity is designed using low power and low offset dynamic comparator. A digital error correction technique using low power XOR logic gate is implemented at the SAR ADC output to minimize the non idealities due to the process variations.

Sign in / Sign up

Export Citation Format

Share Document