Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices

1998 ◽  
Vol 33 (2) ◽  
pp. 302-306 ◽  
Author(s):  
L. Bisdounis ◽  
S. Nikolaidis ◽  
O. Koufopavlou
Keyword(s):  
Transient Response ◽  
Propagation Delay ◽  
Cmos Inverter ◽  
Short Channel

scholarly journals Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Sanjeev Rai ◽  
Jyotsna Sahu ◽  
Wanjul Dattatray ◽  
R. A. Mishra ◽  
Sudarshan Tiwari
Keyword(s):  
Side Wall ◽  
Propagation Delay ◽  
Performance Comparison ◽  
Cmos Inverter ◽  
Short Channel ◽  
Wall Area ◽  
Region I ◽  
Channel Effects ◽  
In Series ◽  
And Performance

The FinFETs recently have been the rallying point for the engineers as far as the development of the technology is concerned. The authors here have tried successfully to compare the performance of 30 nm conventional triple gate (Conv) FinFET structure with that of partially cylindrical (PC) FinFET. In PC-FinFET the fin is divided into two regions. Region I is partially cylindrical and has curvature of half of the fin width, and Region II is like a conventional FinFET (having flat region). The results show that there is considerable improvement in Ion, Ioff, and subsequent suppression of short channel effects, that is, subthreshold slope, DIBL, self heating effect, and so forth. The improvement has also been felt in series resistance in PC-FinFET as compared to C-FinFET. It is noteworthy also to mention that in PC-FinFET the corner of fin is rounded thus reducing the side wall area which further reduces the gate capacitance reducing the intrinsic delay. The DC and transient analysis of CMOS inverter using C-FinFET and PC-FinFET have been done which shows that PC-FinFET inverter has reduced propagation delay as compared to C-FinFET.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

scholarly journals Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

2021 ◽  
Vol 10 (6) ◽  
pp. 1-10
Author(s):  
S.C. Wagaj ◽  
◽  
S.C. Patil ◽  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
Junctionless Transistor ◽  
Dual Gate ◽  
Static Power

In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

scholarly journals SIZING CMOS INVERTERS WITH MILLER EFFECT AND THRESHOLD VOLTAGE VARIATIONS

2006 ◽  
Vol 15 (03) ◽  
pp. 437-454 ◽  
Author(s):  
BORIS ANDREEV ◽  
EDWARD L. TITLEBAUM ◽  
EBY G. FRIEDMAN
Keyword(s):  
Threshold Voltage ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Propagation Delay ◽  
Design Guidelines ◽  
Maximum Speed ◽  
Clock Frequency ◽  
Cmos Inverter ◽  
Worst Case ◽  
Delay Times

The maximum speed of synchronous circuits is generally constrained by the worst case propagation delay, which limits the system clock frequency. Various techniques exist to manage the circuit delay, trading off speed for other system resources. One such approach is to equalize the rise and fall delay times. The primary design parameter for equalizing these delay times is the ratio between the width of the PMOS and NMOS transistors, which determines the relationship between the currents passed along the pull-up and pull-down paths. The variation of the pull-up to pull-down ratio for different circuit parameters is discussed in this paper under the constraint of equal rise and fall delay times. It is shown that the short-circuit current and the Miller capacitance affect the ideal linear relationship between the CMOS inverter delay times and the load capacitance, requiring the pull-up to pull-down ratio to be adjusted as circuit parameters are varied. These effects are more pronounced in deep submicrometer technologies with significant parasitic MOSFET capacitances and threshold voltage variations. Based on analytic and experimental observations, circuit design guidelines are proposed to minimize the Miller effect.

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