Energy-Efficient Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop

2006 ◽  
Author(s):  
Yen-Ting Liu ◽  
Lih-Yih Chiou ◽  
Soon-Jyh Chang
Keyword(s):  
Energy Efficient ◽  
Flip Flop ◽  
Sense Amplifier

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

Sense amplifier based RADHARD flip flop design

2004 ◽  
Vol 51 (6) ◽  
pp. 3811-3815 ◽  
Author(s):  
Weizhong Wang ◽  
Haiyan Gong
Keyword(s):  
Flip Flop ◽  
Sense Amplifier

scholarly journals Multiple purpose spin transfer torque operated devices

2013 ◽  
Vol 26 (3) ◽  
pp. 227-238
Author(s):  
Thomas Windbacher ◽  
Hiwa Mahmoudi ◽  
Alexander Makarov ◽  
Viktor Sverdlov ◽  
Siegfried Selberherr
Keyword(s):  
Information Processing ◽  
Building Block ◽  
Energy Efficient ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Spin Torque ◽  
Logic Device ◽  
Flip Flop ◽  
Sequential Logic ◽  
Efficient Information

We summarize our recent work on a non-volatile logic building block required for energy-efficient information processing systems. A sequential logic device, in particular, an alternative non-volatile magnetic flip-flop has been introduced. Its properties are investigated and its extension to a very dense shift register is demonstrated. We show that the flip-flop structure inherently exhibits oscillations and discuss its spin torque nano-oscillator properties.

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

2018 ◽  
Author(s):  
Kimiyoshi Usami ◽  
Junya Akaike ◽  
Sosuke Akiba ◽  
Masaru Kudo ◽  
Hideharu Amano ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Flip Flop

Cross-Layer Dual Modular Redundancy Hardened Scheme of Flip-Flop Design Based on Sense-Amplifier

2020 ◽  
pp. 2120003
Author(s):  
Zhengfeng Huang ◽  
Zian Su ◽  
Tianming Ni ◽  
Qi Xu ◽  
Haochen Qi ◽  
...  
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Fault Tolerant ◽  
Cross Layer ◽  
Charge Sharing ◽  
Single Node ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Modular Redundancy ◽  
Voltage Swing

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.

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