An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-Flop

2007 ◽  
Author(s):  
Lih-Yih Chiou ◽  
Shien-Chun Lou
Keyword(s):  
Energy Efficient ◽  
Flip Flop

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals Multiple purpose spin transfer torque operated devices

2013 ◽  
Vol 26 (3) ◽  
pp. 227-238
Author(s):  
Thomas Windbacher ◽  
Hiwa Mahmoudi ◽  
Alexander Makarov ◽  
Viktor Sverdlov ◽  
Siegfried Selberherr
Keyword(s):  
Information Processing ◽  
Building Block ◽  
Energy Efficient ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Spin Torque ◽  
Logic Device ◽  
Flip Flop ◽  
Sequential Logic ◽  
Efficient Information

We summarize our recent work on a non-volatile logic building block required for energy-efficient information processing systems. A sequential logic device, in particular, an alternative non-volatile magnetic flip-flop has been introduced. Its properties are investigated and its extension to a very dense shift register is demonstrated. We show that the flip-flop structure inherently exhibits oscillations and discuss its spin torque nano-oscillator properties.

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

2018 ◽  
Author(s):  
Kimiyoshi Usami ◽  
Junya Akaike ◽  
Sosuke Akiba ◽  
Masaru Kudo ◽  
Hideharu Amano ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Flip Flop

An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs

2015 ◽  
Vol E98.A (12) ◽  
pp. 2600-2606
Author(s):  
Yuzuru SHIZUKU ◽  
Tetsuya HIROSE ◽  
Nobutaka KUROKI ◽  
Masahiro NUMA ◽  
Mitsuji OKADA
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Flip Flop ◽  
Ultra Low Power

A Robust and Energy Efficient Pulse-Triggered Flip–Flop Design for Ultra Low Voltage Operations

2014 ◽  
Vol 10 (1) ◽  
pp. 118-126
Author(s):  
Sébastien Bernard ◽  
Alexandre Valentian ◽  
David Bol ◽  
Jean-Didier Legat ◽  
Marc Belleville
Keyword(s):  
Energy Efficient ◽  
Low Voltage ◽  
Flip Flop
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