An abnormal threshold voltage variation of the p-type thin-film transistors under DC bias stress

2015 ◽  
Author(s):  
Han-Wen Liu ◽  
Wei-Fong Cao ◽  
Tsung-Kuei Kang ◽  
Fang-Hsing Wang
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Bias Stress ◽  
Voltage Variation ◽  
Dc Bias ◽  
P Type

Effect of Dynamic Bias Stress (AC) In Short-Channel (L=1.5μm) p-Type polycrystalline Silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate

2011 ◽  
Vol 1321 ◽  
Author(s):  
Sung-Hwan Choi ◽  
Yeon-Gon Mo ◽  
Min-Koo Han
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Glass Substrate ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Short Channel ◽  
Bias Stress ◽  
P Type ◽  
Long Channel ◽  
Si Thin Film

ABSTRACTWe have investigated the stability of short channel (1.5μm) p-Type polycrystalline silicon (poly-Si) Thin Film Transistors (TFTs) on the glass substrate under AC bias stress. The variation of threshold voltage in short channel poly-Si TFT was considerably higher than that of long channel poly-Si TFT. Threshold voltage of the short channel TFT was considerably moved to the positive direction during AC bias stress, whereas the threshold voltage of a long channel was rarely moved. The variation of threshold voltage in the short channel p-type TFT under AC bias stess was more compared to that under DC bias stress. The threshold voltage of short channel (L=1.5μm) poly-Si TFT was increased about -7.44V from -0.305V to -7.745V when VGS = 5 (base value) ~ -15V (peak value), VDS = -15V was applied for 3,000 seconds. This positive shift of threshold voltage and significantly degraded s-swing value in the short channel TFT under dynamic stress (AC) may be due to the increase of the stress-induced trap state density at gate insulator / channel interface region.

Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

2019 ◽  
Vol 28 (8) ◽  
pp. 088502
Author(s):  
Chao-Yang Han ◽  
Yuan Liu ◽  
Yu-Rong Liu ◽  
Ya-Yi Chen ◽  
Li Wang ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Low Frequency ◽  
Frequency Noise ◽  
Gate Bias ◽  
Stress Effects ◽  
Bias Stress ◽  
Noise Characteristics ◽  
P Type ◽  
Si Thin Film

Threshold Voltage Shifts in Amorphous Silicon Thin Film Transistors under Bias Stress

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa
Keyword(s):  
Thin Film ◽  
Temperature Dependence ◽  
Amorphous Silicon ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Charge Trapping ◽  
The Other ◽  
Time Dependent ◽  
Silicon Thin Film ◽  
Bias Stress

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.

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