An on-chip monitor for measuring NBTI degradation of digital circuits

2009 ◽  
Author(s):  
Zheng-yu Zhong ◽  
Min Cai ◽  
Qun-yong Wang ◽  
Na Li
Keyword(s):  
Digital Circuits ◽  
On Chip

Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits

2012 ◽  
Vol E95.A (12) ◽  
pp. 2284-2291 ◽  
Author(s):  
Kumpei YOSHIKAWA ◽  
Yuta SASAKI ◽  
Kouji ICHIKAWA ◽  
Yoshiyuki SAITO ◽  
Makoto NAGATA
Keyword(s):  
Digital Circuits ◽  
Ac Power ◽  
Power Noise ◽  
On Chip

scholarly journals Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

2021 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Narendra Kumar Garg ◽  
Vivek Singh Kushwah ◽  
Manisha Pattanaik
Keyword(s):  
Digital Circuits ◽  
Leakage Power ◽  
Performance Parameters ◽  
New Techniques ◽  
Vlsi Interconnects ◽  
Digital Electronics ◽  
Spice Model ◽  
On Chip ◽  
Carbon Nano Tube ◽  
The Impact

Abstract With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

scholarly journals Fully-integrated LDO voltage regulator for digital circuits

2011 ◽  
Vol 9 ◽  
pp. 263-267 ◽  
Author(s):  
M. Lüders ◽  
B. Eversmann ◽  
D. Schmitt-Landsiedel ◽  
R. Brederlow
Keyword(s):  
Digital Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Maximum Load ◽  
Voltage Regulators ◽  
Ultra Low Power ◽  
Fully Integrated ◽  
Large Current ◽  
Quiescent Current ◽  
On Chip

Abstract. Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a fully-integrated LDO without any external capacitance is preferred in order to achieve a fast and energy-efficient wake-up. Commonly, an LDO is specified, designed and verified for DC load currents. In contrast, a digital load creates large current spikes. As an LDO designed for low quiescent current is too slow to react on fast current spikes, a minimum on-chip capacitance is required to keep the supply voltage within a certain error window. Different fully-integrated LDO topologies are investigated regarding their suitability to supply low-voltage digital circuits. The any-load stable LDO topology is selected and implemented on a 0.13 μm test-chip. The LDO is able to provide a maximum load current of 2.5 mA while consuming a quiescent current of 17 μA.

scholarly journals Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic

2019 ◽  
Vol 8 (2) ◽  
pp. 101-106
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Vlsi Design ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Two Phase ◽  
Adiabatic Logic ◽  
On Chip

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.

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