Inductance: implications and solutions for high-speed digital circuits - on-chip signaling

Author(s):  
S. Morton
Keyword(s):  

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.


Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.


Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.


Author(s):  
Nilanjan Mukherjee ◽  
Artur Pogiel ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  

2011 ◽  
Vol 487 ◽  
pp. 39-43 ◽  
Author(s):  
L. Tian ◽  
Yu Can Fu ◽  
W.F. Ding ◽  
Jiu Hua Xu ◽  
H.H. Su

Single-grain grinding test plays an important part in studying the high speed grinding mechanism of materials. In this paper, a new method and experiment system for high speed grinding test with single CBN grain are presented. In order to study the high speed grinding mechanism of TC4 alloy, the chips and grooves were obtained under different wheel speed and corresponding maximum undeformed chip thickness. Results showed that the effects of wheel speed and chip thickness on chip formation become obvious. The chips were characterized by crack and segment band feature like the cutting segmented chips of titanium alloy Ti6Al4V.


2008 ◽  
Vol 18 (04) ◽  
pp. 913-922 ◽  
Author(s):  
SIDDHARTH RAJAN ◽  
UMESH K. MISHRA ◽  
TOMÁS PALACIOS

This paper provides an overview of recent work and future directions in Gallium Nitride transistor research. We discuss the present status of Ga -polar AlGaN / GaN HEMTs and the innovations that have led to record RF power performance. We describe the development of N -polar AlGaN / GaN HEMTs with microwave power performance comparable with state-of-art Ga -polar AlGaN / GaN HEMTs. Finally we will discuss how GaN -based field effect transistors could be promising for a less obvious application: low-power high-speed digital circuits.


1982 ◽  
Vol 13 (1) ◽  
pp. 29-33 ◽  
Author(s):  
A.W. Livingstone
Keyword(s):  

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