scholarly journals Fully-integrated LDO voltage regulator for digital circuits

2011 ◽  
Vol 9 ◽  
pp. 263-267 ◽  
Author(s):  
M. Lüders ◽  
B. Eversmann ◽  
D. Schmitt-Landsiedel ◽  
R. Brederlow
Keyword(s):  
Digital Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Maximum Load ◽  
Voltage Regulators ◽  
Ultra Low Power ◽  
Fully Integrated ◽  
Large Current ◽  
Quiescent Current ◽  
On Chip

Abstract. Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a fully-integrated LDO without any external capacitance is preferred in order to achieve a fast and energy-efficient wake-up. Commonly, an LDO is specified, designed and verified for DC load currents. In contrast, a digital load creates large current spikes. As an LDO designed for low quiescent current is too slow to react on fast current spikes, a minimum on-chip capacitance is required to keep the supply voltage within a certain error window. Different fully-integrated LDO topologies are investigated regarding their suitability to supply low-voltage digital circuits. The any-load stable LDO topology is selected and implemented on a 0.13 μm test-chip. The LDO is able to provide a maximum load current of 2.5 mA while consuming a quiescent current of 17 μA.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

scholarly journals A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift

2018 ◽  
Vol 27 (08) ◽  
pp. 1850128 ◽  
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
Steve Barker ◽  
Sumathi Raparthy ◽  
Nabil Yassine ◽  
...  
Keyword(s):  
Power Supply ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Temperature Drift ◽  
Ultra Low Power

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65[Formula: see text]nm CMOS has been developed and occupies 0.0039[Formula: see text]mm2, and at room temperature, it generates a 204[Formula: see text]mV reference voltage with 1.3[Formula: see text]mV drift over a wide temperature range (from [Formula: see text]40[Formula: see text]C to 125[Formula: see text]C). This has been designed to operate with a power supply voltage down to 0.6[Formula: see text]V and consumes 1.8[Formula: see text]uA current from the supply. The simulated temperature coefficient is 40[Formula: see text]ppm/[Formula: see text]C.

An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure

2019 ◽  
Vol 28 (10) ◽  
pp. 1950172
Author(s):  
Mehdi Bandali ◽  
Alireza Hassanzadeh ◽  
Masoume Ghashghaie ◽  
Omid Hashemipour
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
The Body ◽  
Current Steering ◽  
Ultra Low Power ◽  
Current Cell ◽  
Sample Rate

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

scholarly journals Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability

2021 ◽  
Author(s):  
Michal Sovcik ◽  
Lukas Nagy ◽  
Viera Stopjakova ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic System ◽  
Digital Calibration ◽  
Electrical Stress ◽  
Offset Voltage ◽  
On Chip ◽  
Analog Systems

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600 mV with 10% variation, in temperature range from − 20 ° C to 85 ° C . Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13 μV to 167 μV . With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.

scholarly journals Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8302
Author(s):  
Cancio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Process Variations ◽  
Cmos Technology ◽  
Process Technology ◽  
Two Phase ◽  
Ultra Low Power ◽  
Ambient Temperatures

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

Low Voltage Low Power Fully Integrated Chaos Generator

2018 ◽  
Vol 27 (10) ◽  
pp. 1850155 ◽  
Author(s):  
Jie Jin ◽  
LV Zhao
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic Components ◽  
Ic Design ◽  
Chip Area ◽  
Fully Integrated ◽  
Chaos Generator ◽  
Wide Range

A low voltage low power fully integrated chaos generator is presented in this paper. Comparing with the conventional off-the-shelf electronic components-based chaos generators, the designed circuit is fully integrated, and it achieves lower supply voltage, lower power dissipation and smaller chip area. The proposed fully integrated chaos generator is verified with GlobalFoundries 0.18[Formula: see text][Formula: see text]m CMOS 1P6M RF process using Cadence IC Design Tools. The simulation results demonstrate that the fully integrated chaos generator consumes only 17[Formula: see text]mW from [Formula: see text]2.5[Formula: see text]V supply voltage. Moreover, the chip area of the chaos generator is only 1.755[Formula: see text]mm2 including the testing pads, and it has a wide range of practical application prospects.

The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

2016 ◽  
pp. 229-251
Author(s):  
Kavyashree P. ◽  
Siva S. Yellampalli
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Low Voltage Operation ◽  
Common Gate ◽  
Low Power Cmos ◽  
Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

Challenges and Limitations of Low Power Techniques

2016 ◽  
pp. 48-70
Author(s):  
Vandana B. ◽  
Patro B. S.
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Semiconductor Device ◽  
Low Voltage ◽  
Supply Voltage ◽  
Oxide Semiconductor ◽  
Gate Length ◽  
Ultra Low Power ◽  
Mos Transistor ◽  
Contemporary World

In contemporary world the technology has kept its vast identity in developing ultra NANO devices to give up the compact device utilities, in VLSI, Metal Oxide Semiconductor device plays an key role in power dissipation product, in terms of MOS theory characteristics it is predefined that a MOS transistor can conduct easily with low voltage which gives low power but in DSM technology there is a likelihood to achieve ultra low power, so this can be achieved due to the rapid shrinking of gate length, here the chapter deals with challenges and limitations of low power techniques. The predominant way to generate low power is to start with the fundamental principles that are defined in the existing technologies that it gives low power with less leakage current. Apart from this parameter consideration is also required to achieve this. The successful and the major parameter in generating low power is that the shrinking of supply voltage. To go through this, upcoming sections gives the brief idea about the different techniques that are utilized to generate low power with less leakage.

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