IC Debug and Defect Localization using Dynamic Laser Stimulation and Time-Resolved Emission

2007 ◽  
Author(s):  
Julie Ferrigno ◽  
Philippe Perdu ◽  
Kevin Sanchez ◽  
Dean Lewis ◽  
Michel Vallet ◽  
...  
Keyword(s):  
Time Resolved ◽  
Laser Stimulation ◽  
Defect Localization

Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device

2012 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille
Keyword(s):  
Mixed Mode ◽  
Laser Stimulation ◽  
Scan Test ◽  
Silicon Bulk ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Test Failure

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

Dual Port RAM MBIST Failure Analysis Using Time Resolved Dynamic Laser Stimulation

2008 ◽  
Author(s):  
Jonathan Shaw ◽  
Christopher McMahon ◽  
Yin Shyang Ng ◽  
Félix Beaudoi
Keyword(s):  
Failure Analysis ◽  
Embedded Memory ◽  
Complementary Information ◽  
Time Resolved ◽  
Laser Stimulation ◽  
Specific Indication ◽  
Read Operation ◽  
Site Localization

Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.

Dynamic Laser Delay Variation Mapping (DVM) Implementations and Applications

2005 ◽  
Author(s):  
Kevin Sanchez ◽  
Romain Desplats ◽  
Philippe Perdu ◽  
Felix Beaudoin ◽  
Sylvain Dudit ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Functional Tests ◽  
Laser Stimulation ◽  
Application Field ◽  
Defect Localization ◽  
Delay Variation

Abstract In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

scholarly journals Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

2020 ◽  
Vol 10 (23) ◽  
pp. 8576
Author(s):  
Han Yang ◽  
Rui Chen ◽  
Jianwei Han ◽  
Yanan Liang ◽  
Yingqi Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Induced Resistance ◽  
Seebeck Effect ◽  
Comprehensive Model ◽  
Induced Voltage ◽  
Efficient Technology ◽  
Resistance Change ◽  
Scanning Velocity ◽  
Laser Stimulation ◽  
Defect Localization

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Precise Defect Localization of Scan Logic Failures by Thermal Laser Stimulation (TLS)

2004 ◽  
Author(s):  
Zhongling Qian ◽  
Christof Brillert ◽  
Christian Burmer ◽  
Peter Egger
Keyword(s):  
Fault Diagnosis ◽  
Analysis Time ◽  
Scan Design ◽  
Additional Method ◽  
Localization Accuracy ◽  
Laser Stimulation ◽  
Defect Localization

Abstract Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.

Product Debug: Speed Problem Related to Unexpected RC Delay

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
F. Zachariasse
Keyword(s):  
Failure Analysis ◽  
Failure Mechanisms ◽  
Audio Signal ◽  
New Product ◽  
Analysis Method ◽  
Standard Analysis ◽  
Time Resolved ◽  
Defect Localization ◽  
Rc Delay ◽  
Comprehensive Study

Abstract In new product designs increasing effort is needed to observe and prove failure mechanisms or process marginalities. For advanced failure analysis Soft Defect Localization (SDL) [1] and Time Resolved Emission (TRE) [2,3] have now become a standard analysis method. Both techniques require a close co-operation between designers and analysts. In this paper we will discuss a comprehensive study to find the mechanism behind a speed problem in the digital part of an audio signal processor. The additional delay was related to unwanted routing through poly-silicide in timing critical circuitry.

Time resolved imaging using synchronous picosecond Photoelectric Laser Stimulation

2006 ◽  
Vol 46 (9-11) ◽  
pp. 1514-1519 ◽  
Author(s):  
A. Douin ◽  
V. Pouget ◽  
M. De Matos ◽  
D. Lewis ◽  
P. Perdu ◽  
...  
Keyword(s):  
Time Resolved ◽  
Laser Stimulation ◽  
Time Resolved Imaging

Timing Problems Due to Spacer Bridging in a Sub-100 nm Product

2008 ◽  
Author(s):  
Jan van Hassel
Keyword(s):  
Atomic Force Microscope ◽  
Yield Loss ◽  
Silicide Formation ◽  
Process Stability ◽  
Time Resolved ◽  
Atomic Force ◽  
Defect Localization ◽  
Lightly Doped Drain ◽  
Modified Test ◽  
Comprehensive Study

Abstract In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.

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