scholarly journals Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

2020 ◽  
Vol 10 (23) ◽  
pp. 8576
Author(s):  
Han Yang ◽  
Rui Chen ◽  
Jianwei Han ◽  
Yanan Liang ◽  
Yingqi Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Induced Resistance ◽  
Seebeck Effect ◽  
Comprehensive Model ◽  
Induced Voltage ◽  
Efficient Technology ◽  
Resistance Change ◽  
Scanning Velocity ◽  
Laser Stimulation ◽  
Defect Localization

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Laser Failure Isolation Techniques Demonstrated On Test Structures

2008 ◽  
Author(s):  
Frank S. Arnold
Keyword(s):  
Integrated Circuits ◽  
Laser Beam ◽  
Case Studies ◽  
Induced Resistance ◽  
Simple Test ◽  
Resistance Change ◽  
Cross Sectional ◽  
Beam Focusing ◽  
Isolation Techniques ◽  
Heating Effects

Abstract To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

Laser Based Defect Localization for the Failure Analysis of Advanced Product

2006 ◽  
Author(s):  
W.Y. Cheng ◽  
T.Y. Chiu ◽  
Jon C. Lee ◽  
J.Y. Chiou
Keyword(s):  
Failure Analysis ◽  
Laser Scanning ◽  
Failure Modes ◽  
Induced Voltage ◽  
Resistance Change ◽  
Thermally Induced ◽  
Defect Localization ◽  
Defect Isolation ◽  
Site Localization ◽  
Selection Of

Abstract Emission microscopy have been used for failure analysis (FA) defect isolation. But for advanced products, the working voltage of chip is getting smaller, thus many emission spots from normal transistors will be observed, which indeed affects the judgment on the emission spots from killer defects and increases the FA difficulty. Laser scanning microscope (LSM)-based techniques have been powerful defect isolation methods for many years. In this study, Checkpoint Infrascan 200TD, a laser-based tool, is used to perform defect localization. Here, thermally induced voltage alteration and optical beam induced resistance change are used to get defect locations. The study demonstrates three FA cases with 80nm/90nm technologies; metal direct short, poly leakage, and contact high resistance are also found in these cases. It is concluded that, by the selection of control parameters, Infrascan 200TD provides several capabilities of failure site localization and can be applied to different failure modes.

A Simple Adapter for Soft Defect Localization Using OBIRCH

2007 ◽  
Author(s):  
Ted Kolasa
Keyword(s):  
Induced Resistance ◽  
Low Cost ◽  
Optical Beam ◽  
Significant Cost ◽  
Resistance Change ◽  
Design Considerations ◽  
Defect Localization

Abstract Equipment manufacturers have developed peripherals for their tools that add soft defect localization (SDL) capability to existing optical beam tools, in many cases providing excellent results. However, these upgrades add significant cost to the tool. This paper presents the design considerations for a simple adapter that was developed in house to add SDL capability to optical beam induced resistance change (OBIRCH) tool, including resolution of some unexpected problems. This solution represents a simple, low cost method to add SDL testing capability to the OBIRCH tool and can also be used in conjunction with OBIC and XIVA tools with little or no modification. An early example of the SDL results provided by this adapter is also presented.

Application of PEM and OBIRCH to Defect Localization of Integrated Circuits

2014 ◽  
Vol 904 ◽  
pp. 277-281
Author(s):  
Jian Wen Lian ◽  
Xiao Ling Lin ◽  
Ruo He Yao
Keyword(s):  
Integrated Circuits ◽  
Failure Mechanisms ◽  
Photon Emission ◽  
Fault Isolation ◽  
Resistance Change ◽  
Microelectronic Devices ◽  
Application Condition ◽  
Defect Localization ◽  
Metal Interconnects ◽  
Fault Characterization

With the increasing integration and complexity of microelectronic devices, fault isolation has been challenged. Photon Emission Microscopy (PEM) and Optical Beam Induced Resistance Change (OBIRCH) are effective tools for defect localization and fault characterization in failure analysis. In this paper, the principles and different application condition of PEM and OBIRCH are discussed. PEM is very helpful for locating defects emitting photon, but can not detect the defects which have no photon emitting, such as shorted metal interconnects; OBIRCH as a complementary, has a high success rate for locating resistance defects. Two cases with failure mechanisms illuminated are presented to show the different application of PEM and OBIRCH.

Laser Beam Based ESD Defect Localization in ICs

2002 ◽  
Author(s):  
Félix Beaudoin ◽  
Philippe Perdu ◽  
Romain Desplats ◽  
Emmanuel Doche ◽  
Alain Wislez ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Laser Beam ◽  
Low Voltage ◽  
Crystalline Silicon ◽  
Physical Analysis ◽  
Molten Silicon ◽  
Laser Stimulation ◽  
Current Consumption ◽  
Defect Localization ◽  
Stimulation Technique

Abstract The application of laser beam based techniques for ESD defect localization in silicon and gallium arsenide integrated circuits is studied. The Thermal Laser Stimulation technique (OBIRCH, TIVA) is shown to precisely localize electrostatic discharge (ESD) defects under low voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline silicon generated a Seebeck voltage sufficiently large to be detected. Finally, the pulsed Optical Beam Induced Current technique (OBIC) under no bias condition was evaluated and compared to both biased and nonbiased Thermal Laser Stimulation techniques. It proved to be complementary as it offers a different insight into the ESD induced degradation.

Beam-Based Defect Localization using Electrons: EBIRCH Overview

2018 ◽  
Author(s):  
Gregory M. Johnson ◽  
Zaheer Khan ◽  
Christopher D’Aleo ◽  
Brian Yates ◽  
Michael Iwatake ◽  
...  
Keyword(s):  
Electron Beam ◽  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Induced Resistance ◽  
Success Rates ◽  
Resistance Change ◽  
Dominant Mechanism ◽  
Defect Localization ◽  
Different Types ◽  
Scanning Electron

Abstract Electron-Beam Induced Resistance CHange (EBIRCH) is a technique that makes use of the electron beam of a scanning electron microscope for defect localization. The beam has an effect on the sample, and the resistance changes resulting from that effect are mapped in the system. This paper explores the beam-based nature of the technique and uses understanding from another beam-based technique, Optical Beam Induced Resistance CHange (OBIRCH), to propose a dominant mechanism. This mechanism may explain the widely different success rates between different types of samples observed after six month’s use of the technique for isolations on large health of line structures in a failure analysis lab.

Improving Amplifier for OBIRCH/TIVA Application

2020 ◽  
Author(s):  
Michael Morag ◽  
Neel Leslie
Keyword(s):  
Induced Resistance ◽  
Optical Beam ◽  
Induced Voltage ◽  
Resistance Change ◽  
Analysis Techniques ◽  
Thermo Fisher Scientific ◽  
Static Conditions ◽  
Fisher Scientific

Abstract OBIRCh(Optical Beam Induced Resistance Change) and TIVA (Thermal Induced Voltage Alteration) are widely used ElectricalFailure Analysis techniques for finding defects under static conditions. This paper will discuss the requirements for a good amplifier to be used for OBIRCh, and recent improvements that have been released to market from Thermo Fisher Scientific.

Case Study: Combined Dynamic Laser Stimulation and Static Emission Microscopy Techniques Applied to Scan Test Failure on Mixed Mode Device

2012 ◽  
Author(s):  
Magdalena Sienkiewicz ◽  
Philippe Rousseille
Keyword(s):  
Mixed Mode ◽  
Laser Stimulation ◽  
Scan Test ◽  
Silicon Bulk ◽  
Defect Localization ◽  
Emission Microscopy ◽  
Microscopy Techniques ◽  
Test Failure

Abstract This paper presents a case study on scan test reject in a mixed mode IC. It focuses on the smart use of combined mature FA techniques, such as Soft Defect Localization (SDL) and emission microscopy (EMMI), to localize a random scan test anomaly at the silicon bulk level.

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