Performance Comparison of Interconnect Technology and Architecture Options for Deep Submicron Technology Nodes

2006 ◽  
Author(s):  
M. Bamal ◽  
S. List ◽  
M. Stucchi ◽  
A.S. Verhulst ◽  
M. Van Hove ◽  
...  
Keyword(s):  
Deep Submicron ◽  
Performance Comparison ◽  
Technology Nodes ◽  
Interconnect Technology

Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond

2009 ◽  
Vol 145-146 ◽  
pp. 253-256 ◽  
Author(s):  
G. Mannaert ◽  
L. Witters ◽  
Denis Shamiryan ◽  
Werner Boullart ◽  
K. Han ◽  
...  
Keyword(s):  
Sheet Resistance ◽  
State Of The Art ◽  
Substrate Oxidation ◽  
Performance Comparison ◽  
Low Energy ◽  
Advanced Technology ◽  
Process Conditions ◽  
Threshold Voltages ◽  
Dopant Loss ◽  
Technology Nodes

The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.

Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP, and WS2-Based n-MOSFETs for Future Technology Nodes—Part I: Device-Level Comparison

2019 ◽  
Vol 66 (8) ◽  
pp. 3608-3613
Author(s):  
Tarun Kumar Agarwal ◽  
Martin Rau ◽  
Iuliana Radu ◽  
Mathieu Luisier ◽  
Wim Dehaene ◽  
...  
Keyword(s):  
Performance Comparison ◽  
Future Technology ◽  
Technology Nodes

scholarly journals Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes—Part II: Circuit-Level Comparison

2019 ◽  
Vol 66 (8) ◽  
pp. 3614-3619
Author(s):  
Tarun Kumar Agarwal ◽  
Martin Rau ◽  
Iuliana Radu ◽  
Mathieu Luisier ◽  
Wim Dehaene ◽  
...  
Keyword(s):  
Performance Comparison ◽  
Future Technology ◽  
Technology Nodes

scholarly journals Failure Localization Techniques for 7nm & 16nm Process Nodes in Monolithic & 2.5D SSIT Package Technology Using OBIRCH, LVP and Advance Die Thinning Method

2021 ◽  
Author(s):  
Daniel Nuez ◽  
Phoumra Tan ◽  
Daisy Lu ◽  
Benhai Zhang ◽  
Joshua Miller ◽  
...  
Keyword(s):  
Spatial Resolution ◽  
High Performance ◽  
Semiconductor Industry ◽  
Diagnostic Techniques ◽  
Diagnostic Equipment ◽  
Technology Nodes ◽  
Thinning Process ◽  
Interconnect Technology ◽  
Preparation Techniques ◽  
Failure Localization

Abstract High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.

scholarly journals Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

2004 ◽  
Vol 35 (10) ◽  
pp. 849-857 ◽  
Author(s):  
Mariagrazia Graziano ◽  
Mario R. Casu ◽  
Guido Masera ◽  
Gianluca Piccinini ◽  
Maurizio Zamboni
Keyword(s):  
Deep Submicron ◽  
Future Technology ◽  
Interconnect Optimization ◽  
Effects Of Temperature ◽  
Global Interconnect ◽  
Technology Nodes

scholarly journals Impact of Bundle Structure on Performance of on-Chip CNT Interconnects

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Nisha Kuruvilla ◽  
J. P. Raina
Keyword(s):  
Deep Submicron ◽  
Worst Case ◽  
Optimum Performance ◽  
Future Technology ◽  
Performance Predictions ◽  
Metallic Cnts ◽  
Swcnts And Mwcnts ◽  
On Chip ◽  
Technology Nodes ◽  
Bundle Structure

CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.

Sign in / Sign up

Export Citation Format

Share Document