Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP, and WS2-Based n-MOSFETs for Future Technology Nodes—Part I: Device-Level Comparison

2019 ◽  
Vol 66 (8) ◽  
pp. 3608-3613
Author(s):  
Tarun Kumar Agarwal ◽  
Martin Rau ◽  
Iuliana Radu ◽  
Mathieu Luisier ◽  
Wim Dehaene ◽  
...  
Keyword(s):  
Performance Comparison ◽  
Future Technology ◽  
Technology Nodes

scholarly journals Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes—Part II: Circuit-Level Comparison

2019 ◽  
Vol 66 (8) ◽  
pp. 3614-3619
Author(s):  
Tarun Kumar Agarwal ◽  
Martin Rau ◽  
Iuliana Radu ◽  
Mathieu Luisier ◽  
Wim Dehaene ◽  
...  
Keyword(s):  
Performance Comparison ◽  
Future Technology ◽  
Technology Nodes

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Reduction of CNT Interconnect Resistance for the Replacement of Cu for Future Technology Nodes

2012 ◽  
Vol 11 (1) ◽  
pp. 56-62 ◽  
Author(s):  
Jonathan W. Ward ◽  
Jonathan Nichols ◽  
Timothy B. Stachowiak ◽  
Quoc Ngo ◽  
E. James Egerton
Keyword(s):  
Future Technology ◽  
Technology Nodes ◽  
Interconnect Resistance

Photomask etch challenges for future technology nodes

2006 ◽  
Author(s):  
Madhavi Chandrachood ◽  
Michael Grimbergen ◽  
Toi Yue B. Leung ◽  
Keven Yu ◽  
Renee Koch ◽  
...  
Keyword(s):  
Future Technology ◽  
Technology Nodes

scholarly journals Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 53196-53202 ◽  
Author(s):  
Daniel Nagy ◽  
Gabriel Espineira ◽  
Guillermo Indalecio ◽  
Antonio J. Garcia-Loureiro ◽  
Karol Kalna ◽  
...  
Keyword(s):  
Future Technology ◽  
Technology Nodes

Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond

2009 ◽  
Vol 145-146 ◽  
pp. 253-256 ◽  
Author(s):  
G. Mannaert ◽  
L. Witters ◽  
Denis Shamiryan ◽  
Werner Boullart ◽  
K. Han ◽  
...  
Keyword(s):  
Sheet Resistance ◽  
State Of The Art ◽  
Substrate Oxidation ◽  
Performance Comparison ◽  
Low Energy ◽  
Advanced Technology ◽  
Process Conditions ◽  
Threshold Voltages ◽  
Dopant Loss ◽  
Technology Nodes

The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

2021 ◽  
Author(s):  
Fahimul Islam Sakib ◽  
Md. Azizul Hasan ◽  
Mainul Hossain
Keyword(s):  
Performance Optimization ◽  
Computer Aided Design ◽  
Single Channel ◽  
Field Effect Transistors ◽  
Three Dimensional ◽  
Differential Resistance ◽  
Future Technology ◽  
Aided Design ◽  
Technology Nodes ◽  
Tcad Simulations

Abstract Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (ION ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher ION/IOFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

Sign in / Sign up

Export Citation Format

Share Document