scholarly journals Impact of Bundle Structure on Performance of on-Chip CNT Interconnects

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Nisha Kuruvilla ◽  
J. P. Raina
Keyword(s):  
Deep Submicron ◽  
Worst Case ◽  
Optimum Performance ◽  
Future Technology ◽  
Performance Predictions ◽  
Metallic Cnts ◽  
Swcnts And Mwcnts ◽  
On Chip ◽  
Technology Nodes ◽  
Bundle Structure

CNTs are proposed as a promising candidate against copper in deep submicron IC interconnects. Still this technology is in its infancy. Most available literatures on performance predictions of CNT interconnects, have focused only on interconnect geometries using segregated CNTs. Yet during the manufacturing phase, CNTs are obtained usually as a mixture of single-walled and multi-walled CNTs (SWCNTs and MWCNTs). Especially in case of SWCNTs; it is usually available as a mixture of both Semi conducting CNTs and metallic CNTs. This paper attempts to answer whether segregation is inevitable before using them to construct interconnects. This paper attempt to compare the performance variations of bundled CNT interconnects, where bundles are made of segregated CNTs versus mixed CNTs, for future technology nodes using electrical model based analysis. Also a proportionate mixing of different CNTs has been introduced so as to yield a set of criteria to aid the industry in selection of an appropriate bundle structure for use in a specific application with optimum performance. It was found that even the worst case performance of geometries using a mixture of SWCNTs and MWCNTs was better than copper. These results also reveal that, for extracting optimum performance vide cost matrix, the focus should be more on diameter controlled synthesis than on segregation.

scholarly journals VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-23 ◽  
Author(s):  
Gottfried Fuchs ◽  
Andreas Steininger
Keyword(s):  
Fault Tolerant ◽  
Single Point ◽  
Asynchronous Design ◽  
Clock Generation ◽  
Future Technology ◽  
Novel Approach ◽  
Measurement Results ◽  
Crystal Oscillators ◽  
On Chip ◽  
Technology Nodes

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply–properties that are considered highly desirable for future technology nodes.

scholarly journals Effects of temperature in deep-submicron global interconnect optimization in future technology nodes

2004 ◽  
Vol 35 (10) ◽  
pp. 849-857 ◽  
Author(s):  
Mariagrazia Graziano ◽  
Mario R. Casu ◽  
Guido Masera ◽  
Gianluca Piccinini ◽  
Maurizio Zamboni
Keyword(s):  
Deep Submicron ◽  
Future Technology ◽  
Interconnect Optimization ◽  
Effects Of Temperature ◽  
Global Interconnect ◽  
Technology Nodes

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

2013 ◽  
Vol 21 (10) ◽  
pp. 1823-1836 ◽  
Author(s):  
Yiyuan Xie ◽  
Mahdi Nikdast ◽  
Jiang Xu ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Networks ◽  
Case Analysis ◽  
Worst Case Analysis ◽  
Crosstalk Noise ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip

Effect of B dose and Ge preamorphization energy on the electrical and structural properties of ultrashallow junctions in silicon-on-insulator

2006 ◽  
Vol 912 ◽  
Author(s):  
Justin J Hamilton ◽  
Erik JH Collart ◽  
Benjamin Colombeau ◽  
Massimo Bersani ◽  
Damiano Giubertoni ◽  
...  
Keyword(s):  
Structural Properties ◽  
Solid Phase ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Bulk Silicon ◽  
Defect Band ◽  
Future Technology ◽  
Ultrashallow Junctions ◽  
P Type ◽  
Technology Nodes

AbstractFormation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next generations of CMOS devices, particularly for source-drain extensions. For p-type dopant implants (boron), a promising method of increasing junction abruptness is to use Ge preamorphizing implants prior to ultra-low energy B implantation and solid-phase epitaxy regrowth to re-crystallize the amorphous Si. However, for future technology nodes, new issues arise when bulk silicon is supplanted by silicon-on-insulator (SOI). Previous results have shown that the buried Si/SiO2 interface can improve dopant activation, but the effect depends on the detailed preamorphization conditions and further optimization is required. In this paper a range of B doses and Ge energies have been chosen in order to situate the end-of-range (EOR) defect band at various distances from the back interface of the active silicon film (the interface with the buried oxide), in order to explore and optimize further the effect of the interface on dopant behavior. Electrical and structural properties were measured by Hall Effect and SIMS techniques. The results show that the boron deactivates less in SOI material than in bulk silicon, and crucially, that the effect increases as the distance from the EOR defect band to the back interface is decreased. For the closest distances, an increase in junction steepness is also observed, even though the B is located close to the top surface, and thus far from the back interface. The position of the EOR defect band shows the strongest influence for lower B doses.

Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

2006 ◽  
Vol 970 ◽  
Author(s):  
Manabu Bonkohara ◽  
Makoto Motoyoshi ◽  
Kazutoshi Kamibayashi ◽  
Mitsumasa Koyanagi
Keyword(s):  
Three Dimensional ◽  
Process Time ◽  
Future Technology ◽  
Sensor Device ◽  
Research Level ◽  
Key Technologies ◽  
The Future ◽  
Chip Size ◽  
On Chip ◽  
Chip Chip

ABSTRACTRecently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Reduction of CNT Interconnect Resistance for the Replacement of Cu for Future Technology Nodes

2012 ◽  
Vol 11 (1) ◽  
pp. 56-62 ◽  
Author(s):  
Jonathan W. Ward ◽  
Jonathan Nichols ◽  
Timothy B. Stachowiak ◽  
Quoc Ngo ◽  
E. James Egerton
Keyword(s):  
Future Technology ◽  
Technology Nodes ◽  
Interconnect Resistance

Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

2012 ◽  
pp. 201-230
Author(s):  
Zhenyu Qi ◽  
Yan Zhang ◽  
Mircea Stan
Keyword(s):  
Design Parameters ◽  
Worst Case Analysis ◽  
Transimpedance Amplifier ◽  
Large Area ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Adaptive Computation ◽  
Bias Temperature Instability ◽  
Computation Efficiency ◽  
On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

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