Process integration of Cu metallization and ultra low k (k=2.2)

2003 ◽  
Author(s):  
Chuan-cheng Cheng ◽  
Wei-jen Hsia ◽  
J. Pallinti ◽  
S. Neumann ◽  
J. Koh ◽  
...  
Keyword(s):  
Process Integration ◽  
Cu Metallization ◽  
Low K

UV-Raman Microscopy on the Analysis of Ultra-Low-K Dielectric Materials on Patterned Wafers

2013 ◽  
Vol 740 ◽  
pp. 680-689 ◽  
Author(s):  
Maggie Y.M. Huang ◽  
Jeffrey C.K. Lam ◽  
Hao Tan ◽  
Tsu Hau Ng ◽  
Mohammed Khalid Bin Dawood ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Process Integration ◽  
Dielectric Materials ◽  
Raman Microscopy ◽  
Three Dimension ◽  
Cu Metallization ◽  
Patterned Wafers ◽  
Uv Raman ◽  
Low K

With the shrinkage of the IC device dimension, Cu and ultra-low-k dielectric were introduced into IC devices to reduce the RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

UV-Raman Microscopy on the Analysis of Ultra-Low-k Dielectric Materials on Patterned Wafers

2013 ◽  
Author(s):  
Maggie Y.M. Huang ◽  
Tsu Hau Ng ◽  
Hao Tan ◽  
Mohammed Khalid Bin Dawood ◽  
Pik Kee Tan ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Dielectric Breakdown ◽  
Process Integration ◽  
Dielectric Materials ◽  
Raman Microscopy ◽  
Three Dimension ◽  
Cu Metallization ◽  
Patterned Wafers ◽  
Uv Raman ◽  
Low K

Abstract With the shrinkage of the IC device dimensions, Cu and ultra-low-k dielectric were introduced into IC devices to reduce RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.

Delamination Behavior of Cu-Low-k Stack Under Different Slurries

2003 ◽  
Vol 767 ◽  
Author(s):  
A. K. Sikder ◽  
S. Thagella ◽  
P. B. Zantye ◽  
Ashok Kumar
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Chemical Mechanical Polishing ◽  
Wear Behavior ◽  
Polished Surface ◽  
Cu Metallization ◽  
Wide Range ◽  
Low K ◽  
Delamination Behavior ◽  
Scanning Electron

AbstractLower mechanical strength, reduced cohesive strength and lack of compatibility with other interconnect materials, are the major challenges involved in chemical mechanical polishing (CMP) of Cu metallization with ultra low-k materials as interlayer dielectrics. In this study we have investigated the polishing behavior of patterned Cu samples with underneath different low-k materials using two different slurries and a wide range of machine parameters. CMP micro tribometer was used to polish the samples with different rotations of platen (50 to 250 RPM) and down forces (1-6 PSI). Friction co-efficient and wear behavior were also investigated at different conditions. Optical and scanning electron microscopy was used to investigate the polished surface. It was observed that the two different Cu slurries used for polishing have marked effects on the polishing of Cu-low-k stack with respect to wear and delamination.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Diffusion Barriers For Fluorinated Low-k Dielectrics

1999 ◽  
Vol 565 ◽  
Author(s):  
M. DelaRosa ◽  
A. Kumar ◽  
H. Bakhru ◽  
T.-M. Lu
Keyword(s):  
Barrier Layer ◽  
Process Integration ◽  
Diffusion Barriers ◽  
Copper Interconnects ◽  
Nuclear Reaction Analysis ◽  
Fluorine Concentration ◽  
Dielectric Barrier ◽  
Barrier Materials ◽  
Teflon Af ◽  
Low K

AbstractThe fluorinated low-k dielectrics SiO:F and Teflon AF were investigated for process integration with aluminum and copper interconnects. To minimize fluorine diffusion, several potential barrier materials were deposited onto the fluorinated dielectrics and characterized after heat treatment at temperatures up to 450°C. The barrier layers studied include conventional materials such as Ta, TaN, and TiN, in addition to several novel materials. Barrier layer materials were deposited using evaporation, and sputtering. The materials were characterized using nuclear reaction analysis (NRA) to determine the fluorine concentration profile. A reaction zone was noted at the dielectric-barrier interface on several samples, corresponding to the formation of a fluoride complex. In some instances, this fluoride layer was self-limiting and prevented further fluorine diffusion through the remainder of the barrier layer.

Methods And Needs For Low K Material Research

1995 ◽  
Vol 381 ◽  
Author(s):  
Chiu H. Ting ◽  
Thomas E. Seidel
Keyword(s):  
High Performance ◽  
Process Integration ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Material Research ◽  
Material Development ◽  
Device Reliability ◽  
New Material ◽  
Speed Up ◽  
Low K

AbstractFor several years the industry has recognized the need of developing low k dielectric material and high conductivity metal for high performance interconnect. Low k dielectric will impact both power and delay favorably, while higher conductivity metal will reduce delay time. In order to be useful, new low k dielectric materials must be carefully characterized for their electrical, chemical, thermal and mechanical properties. In addition, their impact on process integration, fabrication cost and device reliability must also be considered. Since the gestation period for introducing a new material is very long, a set of standard testing methodologies are required to speed up the development process. This review will discuss various material options and the progress of material development and characterization methodologies. Example results will be provided for assessing these parameters.

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