Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS

2006 ◽  
Author(s):  
E. Yoshida ◽  
Y. Momiyama ◽  
M. Miyamoto ◽  
T. Saiki ◽  
M. Kojima ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Device Design ◽  
New Device ◽  
Low Power Cmos

Design methodology of low-power CMOS RF-ICs

2003 ◽  
Author(s):  
Tsuneo Tsukahara ◽  
Mitsuru Harada ◽  
Mamoru Ugajin ◽  
Junichi Kodate ◽  
Akihirro Yamagishi
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Cmos ◽  
Cmos Rf ◽  
Rf Ics

A new device design methodology for manufacturability

1998 ◽  
Vol 45 (3) ◽  
pp. 634-642 ◽  
Author(s):  
J.-C. Lu ◽  
W.C. Holton ◽  
J.S. Fenner ◽  
S.C. Williams ◽  
K.W. Kim ◽  
...  
Keyword(s):  
Design Methodology ◽  
Device Design ◽  
New Device

scholarly journals A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

2011 ◽  
Vol 6 (1) ◽  
pp. 7-17
Author(s):  
Dalton Colombo ◽  
Christian Fayomi ◽  
Frederic Nabki ◽  
Luiz F. Ferreira ◽  
Gilson Wirth ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Analog Design ◽  
Voltage Reference ◽  
Inversion Coefficient ◽  
Low Power Cmos ◽  
Traditional Approaches

This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

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