Design and implementation of a high-speed and area-efficient viterbi decoder

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings ◽

10.1109/icsict.2006.306631 ◽

2006 ◽

Cited By ~ 1

Author(s):

Hao Yang ◽

Xiao-lang Yan

Keyword(s):

High Speed ◽

Viterbi Decoder ◽

Design And Implementation ◽

Area Efficient

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Design and Implementation of High Speed and Area Efficient MAC Unit

International Journal of MC Square Scientific Research ◽

10.20894/ijmsr.117.009.001.014 ◽

2017 ◽

Vol 9 (1) ◽

pp. 117-129

Author(s):

M. Nivedha ◽

◽

V. Priyadharshini ◽

Keyword(s):

High Speed ◽

Design And Implementation ◽

Area Efficient

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VLSI Design and Implementation of a High-Speed Viterbi Decoder

Journal of Computer Research and Development ◽

10.1360/crad20071222 ◽

2007 ◽

Vol 44 (12) ◽

pp. 2143 ◽

Cited By ~ 1

Author(s):

Qing Li

Keyword(s):

High Speed ◽

Vlsi Design ◽

Viterbi Decoder ◽

Design And Implementation

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VLSI design and implementation of high-speed Viterbi decoder

IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions ◽

10.1109/icccas.2002.1180573 ◽

2003 ◽

Cited By ~ 2

Author(s):

Yu-xin You ◽

Jin-xiang Wang ◽

Feng-chang Lai ◽

Yi-zheng Ye

Keyword(s):

High Speed ◽

Vlsi Design ◽

Viterbi Decoder ◽

Design And Implementation

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Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA

International Journal of Computer Applications ◽

10.5120/9246-3410 ◽

2012 ◽

Vol 58 (1) ◽

pp. 17-21 ◽

Cited By ~ 1

Author(s):

S. V.Padmajarani ◽

M. Muralidhar

Keyword(s):

High Speed ◽

Design And Implementation ◽

Parallel Prefix ◽

Prefix Adder ◽

Area Efficient

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Real-time area efficient and high speed architecture design of Viterbi decoder

2016 2nd International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB) ◽

10.1109/aeeicb.2016.7538282 ◽

2016 ◽

Cited By ~ 1

Author(s):

Amitava Middya ◽

Anindya S. Dhar

Keyword(s):

Real Time ◽

High Speed ◽

Architecture Design ◽

Viterbi Decoder ◽

Area Efficient

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High speed area efficient configurable Viterbi Decoder for WiFi and WiMAX systems

2007 International Conference on Intelligent and Advanced Systems ◽

10.1109/icias.2007.4658614 ◽

2007 ◽

Cited By ~ 5

Author(s):

Sridhar Nandula ◽

Yepuri Sudhakara Rao ◽

Siva Prasad Embanath

Keyword(s):

High Speed ◽

Viterbi Decoder ◽

Area Efficient

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Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems ◽

10.1109/vlsid.2014.67 ◽

2014 ◽

Cited By ~ 1

Author(s):

Narayan V. Sugur ◽

Saroja V. Siddamal ◽

Samba Sivam Vemala

Keyword(s):

High Throughput ◽

Viterbi Decoder ◽

Design And Implementation ◽

Hard Decision ◽

Area Efficient

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Design and Implementation of High Speed Viterbi Decoder and Convolution Encoder for SDR

Indian Journal of Science and Technology ◽

10.17485/ijst/2019/v12i36/147574 ◽

2019 ◽

Vol 12 (36) ◽

pp. 1-5

Author(s):

Reshmi R. J. ◽

Raji C

Keyword(s):

High Speed ◽

Viterbi Decoder ◽

Design And Implementation

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Design and Implementation of Low Power High Speed Viterbi Decoder

Procedia Engineering ◽

10.1016/j.proeng.2012.01.834 ◽

2012 ◽

Vol 30 ◽

pp. 61-68 ◽

Cited By ~ 1

Author(s):

K. Cholan

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder ◽

Design And Implementation

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Design and Implementation of High Speed 64-Bit Multiply and Accumulator Unit Using FPGA

International Journal of Innovative Research in Computer and Communication Engineering ◽

10.15680/ijircce.2015.0305022 ◽

2015 ◽

Vol 03 (05) ◽

pp. 3889-3896 ◽

Cited By ~ 1

Author(s):

Dipika Chauhan, Prof. Kinjal va gadia, Prof. Kirit Patel

Keyword(s):

High Speed ◽

Design And Implementation

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