scholarly journals Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA

2012 ◽  
Vol 58 (1) ◽  
pp. 17-21 ◽  
Author(s):  
S. V.Padmajarani ◽  
M. Muralidhar
Keyword(s):  
High Speed ◽  
Design And Implementation ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Area Efficient

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies

2013 ◽  
Vol 42 (7) ◽  
pp. 731-743 ◽  
Author(s):  
Stefania Perri ◽  
Marco Lanuzza ◽  
Pasquale Corsonello
Keyword(s):  
Low Power ◽  
High Speed ◽  
Parallel Prefix ◽  
Prefix Adder

scholarly journals Design a High Speed Multiplier using Two Phase PPA

2019 ◽  
Vol 8 (11S2) ◽  
pp. 146-149
Keyword(s):  
High Speed ◽  
Two Phase ◽  
Ripple Carry Adder ◽  
Product Generation ◽  
Different Types ◽  
Effective System ◽  
Parallel Prefix ◽  
Three Stages ◽  
Prefix Adder ◽  
Prefix Adders

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

scholarly journals Design of High Speed Advanced Encryption Standard using PPA and PPM

2019 ◽  
Vol 8 (9) ◽  
pp. 2679-2684
Keyword(s):  
High Speed ◽  
Block Cipher ◽  
Internet Security ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Fundamental Goal ◽  
Parallel Prefix ◽  
Encoding Strategies ◽  
Prefix Adder ◽  
Symmetric Block

Basically, internet security plays crucial role in past three decades. So in worldwide Advanced Encryption Standard (AES) algorithm is used. AES consists of symmetric block cipher blocks. In this paper we proposed the simplified AES algorithm (S-DES) using parallel prefix adder (PPA) and parallel prefix multiplier (PPM). This parallel prefix adder and parallel prefix multiplier will generate a product formed by multiplying the multiplicand. This algorithm possess specific structure to encrypt and decrypt delicate information and is connected in equipment and programming everywhere throughout the world. It is amazingly hard to programmers to get the genuine information while encoding the AES calculation. The fundamental goal of this algorithm is to build up a model that is executed for correspondence reason, and to test the created model regarding precision reason. The encryption procedure comprises the mix of different traditional methods, for example, substitution, improvement and change encoding strategies. At last the key extension module will comprise the quantity of iterative preparing rounds so as to expand its resistance against unapproved assaults.

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