Design and Implementation of Low Power High Speed Viterbi Decoder

Procedia Engineering ◽

10.1016/j.proeng.2012.01.834 ◽

2012 ◽

Vol 30 ◽

pp. 61-68 ◽

Cited By ~ 1

Author(s):

K. Cholan

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder ◽

Design And Implementation

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A high-speed low-power pipelined Viterbi Decoder: breaking the ACS-bottleneck

The 2010 International Conference on Green Circuits and Systems ◽

10.1109/icgcs.2010.5543044 ◽

2010 ◽

Cited By ~ 7

Author(s):

Kelvin Yi-Tse Lai

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder

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Design and Implementation of High-Speed Low-Power Carry Select Adder

10.1007/978-981-16-1056-1_41 ◽

2021 ◽

pp. 517-530

Author(s):

Kummetha Deepthi ◽

Pratheeksha Bhaskar ◽

M. Priyanka ◽

B. V. Sonika ◽

B. N. Shashikala

Keyword(s):

Low Power ◽

High Speed ◽

Design And Implementation ◽

Carry Select Adder

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Design and Implementation of 3-bit Flash Analog to Digital Converter for Low Power and High Speed Applications with New Ex-OR Based ROM Encoder

Lecture Notes in Electrical Engineering - Advances in Electrical and Computer Technologies ◽

10.1007/978-981-15-9019-1_53 ◽

2021 ◽

pp. 613-626

Author(s):

S. S. Kamate ◽

H. P. Rajani

Keyword(s):

Low Power ◽

High Speed ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Design And Implementation

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838266 ◽

2005 ◽

Vol 52 (2) ◽

pp. 350-365 ◽

Cited By ~ 19

Author(s):

Man Guo ◽

M.O. Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation

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VLSI implementation of a high-speed and low-power punctured Viterbi decoder

2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings. ◽

10.1109/tencon.2002.1180342 ◽

2003 ◽

Author(s):

Li Qiao ◽

You Yuxin ◽

Wang Jinxiang ◽

Ye Yizheng

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Viterbi Decoder

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Design and Implementation of High-Speed Low Power Multipliers Using Reversible Logic

INTERNATIONAL JOURNAL OF EMERGING TRENDS IN SCIENCE AND TECHNOLOGY ◽

10.18535/ijetst/v3i05.05 ◽

2016 ◽

Author(s):

Koustuv Chakraborty ◽

Keyword(s):

Low Power ◽

High Speed ◽

Reversible Logic ◽

Design And Implementation

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High Speed Low-Power Viterbi Decoder Using Trellis Code Modulation

International Journal of Computing Algorithm ◽

10.20894/ijcoa.101.005.001.013 ◽

2016 ◽

Vol 5 (1) ◽

pp. 55-58

Author(s):

K. Neelaveni ◽

◽

G. Saravanakumar ◽

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder ◽

Trellis Code ◽

Code Modulation

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An efficient metric normalization architecture for high-speed low-power viterbi decoder

TENCON 2007 - 2007 IEEE Region 10 Conference ◽

10.1109/tencon.2007.4429152 ◽

2007 ◽

Cited By ~ 2

Author(s):

Kelvin Yi-Tse Lai

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder

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High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2011.2111392 ◽

2012 ◽

Vol 20 (4) ◽

pp. 755-759 ◽

Cited By ~ 23

Author(s):

Jinjin He ◽

Huaping Liu ◽

Zhongfeng Wang ◽

Xinming Huang ◽

Kai Zhang

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder ◽

Decoder Design

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The Design of High-Speed and Low Power Consumption Bidirection Viterbi Decoder

2006 International Conference on Machine Learning and Cybernetics ◽

10.1109/icmlc.2006.258740 ◽

2006 ◽

Cited By ~ 2

Author(s):

Song Li ◽

Qing-ming Yi

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Low Power Consumption ◽

Viterbi Decoder

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