Hardware Implementation of 64B/66B Encoder/Decoder for 10-Gigabit Ethernet

2006 ◽  
Author(s):  
Zhou Qinglun ◽  
Li Chunyan ◽  
Wang Yong
Keyword(s):  
Hardware Implementation ◽  
Gigabit Ethernet ◽  
10 Gigabit Ethernet

Implementation of CRC in 10-Gigabit Ethernet Based on FPGA

2014 ◽  
Vol 599-601 ◽  
pp. 1548-1552
Author(s):  
Bin Li ◽  
Zhi Ping Huang ◽  
Shao Jing Su ◽  
Jun Peng Hu
Keyword(s):  
Traditional Method ◽  
Environmental Constraints ◽  
Data Input ◽  
Gigabit Ethernet ◽  
Parallel Data ◽  
Quartus Ii ◽  
Parallel Input ◽  
10 Gigabit Ethernet

This paper describes the algorithm principle of CRC-32 codes, and then proposes multiple bits parallel input to achieve CRC-32 checksum on the basis of the principle. To design modules using VHDL language in Quartus II environment based on Altera’s EP4SGX230KF40C2 chip. Compared to traditional method of serial and 8 bits parallel data input, implementation of the program integrates 16, 32 and 64 bits parallel data input modes, the user can select the appropriate modules according to their needs and environmental constraints, which will greatly enhance the ability to adapt to the system and meet the needs of a variety of environments.

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