Impact of inductance on timing characteristics of VLSI interconnects

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) ◽

10.1109/iccdcs.2000.869801 ◽

2002 ◽

Author(s):

G. Servel ◽

F. Huret ◽

E. Paleczny ◽

P. Kennis ◽

D. Deschacht

Keyword(s):

Vlsi Interconnects

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Highly accurate analytic model for admittance matrix calculation of VLSI interconnects in CMOS technology

Microprocessors and Microsystems ◽

10.1016/s0141-9331(02)00025-x ◽

2002 ◽

Author(s):

H Ymeri

Keyword(s):

Cmos Technology ◽

Analytic Model ◽

Vlsi Interconnects ◽

Admittance Matrix ◽

Matrix Calculation

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Fast method for frequency and time domain simulation of high-speed VLSI interconnects.

10.22215/etd/1994-02826 ◽

1994 ◽

Author(s):

Ramin Sanaie

Keyword(s):

Time Domain ◽

High Speed ◽

Fast Method ◽

Time Domain Simulation ◽

Vlsi Interconnects

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Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects

Thirteenth International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2012.6187508 ◽

2012 ◽

Cited By ~ 3

Author(s):

Manoj Kumar Majumder ◽

Nisarg D. Pandya ◽

B. K. Kaushik ◽

S. K. Manhas

Keyword(s):

Vlsi Interconnects

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Novel Fabrication of Carbon Nanotube Vias for VLSI Interconnects

Microscopy and Microanalysis ◽

10.1017/s1431927608084055 ◽

2008 ◽

Vol 14 (S2) ◽

pp. 298-299

Author(s):

J Wu ◽

J Walenza-Slabe ◽

M Mann ◽

KBK Teo ◽

WI Milne ◽

...

Keyword(s):

New Mexico ◽

Carbon Nanotube ◽

Vlsi Interconnects

Extended abstract of a paper presented at Microscopy and Microanalysis 2008 in Albuquerque, New Mexico, USA, August 3 – August 7, 2008

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Packaging design support environment-a simulation system for analysis of VLSI interconnects

Ninth Annual International Phoenix Conference on Computers and Communications. 1990 Conference Proceedings ◽

10.1109/pccc.1990.101705 ◽

1990 ◽

Cited By ~ 2

Author(s):

T.D. Whipple ◽

J.W. Rozenblit ◽

J.L. Prince ◽

O.A. Palusinski

Keyword(s):

Simulation System ◽

Design Support ◽

Packaging Design ◽

Vlsi Interconnects ◽

Design Support Environment

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Using Multiple Scales Method to calculate threshold crossing time for the ramp response for high inductance VLSI interconnects

2008 12th IEEE Workshop on Signal Propagation on Interconnects ◽

10.1109/spi.2008.4558391 ◽

2008 ◽

Author(s):

Agnieszka Ligocka ◽

Wojciech Bandurski

Keyword(s):

Multiple Scales ◽

Multiple Scales Method ◽

Vlsi Interconnects ◽

Threshold Crossing ◽

Crossing Time ◽

Ramp Response

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Analysis of propagation delay in mixed carbon nanotube bundle as global VLSI interconnects

2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics ◽

10.1109/primeasia.2012.6458638 ◽

2012 ◽

Cited By ~ 3

Author(s):

Pankaj Kumar Das ◽

Manoj Kumar Majumder ◽

B. K. Kaushik ◽

S. Dasgupta

Keyword(s):

Carbon Nanotube ◽

Propagation Delay ◽

Vlsi Interconnects ◽

Nanotube Bundle

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Statistical Simulation and Optimization of High-Speed VLSI Interconnects

Modeling and Simulation of High Speed VLSI Interconnects ◽

10.1007/978-1-4615-2718-3_10 ◽

1994 ◽

pp. 95-106

Author(s):

Qi-Jun Zhang ◽

M. S. Nakhla

Keyword(s):

High Speed ◽

Statistical Simulation ◽

Simulation And Optimization ◽

Vlsi Interconnects

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On-chip inductance modeling of VLSI interconnects

2000 IEEE International Solid-State Circuits Conference Digest of Technical Papers ◽

10.1109/isscc.2000.839736 ◽

2002 ◽

Author(s):

Xiaoning Qi ◽

B. Kleveland ◽

Zhiping Yu ◽

S. Wong ◽

R. Dutton ◽

...

Keyword(s):

Vlsi Interconnects ◽

On Chip

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Analysis of Equal and Unequal Transition Time Effects on Power Dissipation in Coupled VLSI Interconnects

Advances in Intelligent and Soft Computing - Advances in Computer Science, Engineering & Applications ◽

10.1007/978-3-642-30157-5_15 ◽

2012 ◽

pp. 137-144

Author(s):

Devendra Kumar Sharma ◽

Brajesh Kumar Kaushik ◽

Richa K. Sharma

Keyword(s):

Power Dissipation ◽

Transition Time ◽

Time Effects ◽

Vlsi Interconnects

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