Iterative built-in testing and tuning of mixed-signal/RF systems

Abstract A rapid prototyping method for designing mixed signal systems has been presented in the paper. The method is based on implementation of the field programmable analog array (FPAA) to configure and reconfigure mixed signal systems. A serial algorithmic analog digital converter has been used as an example. Three converter architectures have been selected and implemented FPAA device. To verify and illustrate converters operation and prototyping capabilities, implemented converters have been excited by a sinusoidal signal. Analog sinusoidal excitations, digital responses and sinusoidal waveforms after reconstruction are presented.

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Arithmetic Compactors Design: Application to Mixed Signal Systems

i-manager’s Journal on Embedded Systems ◽

10.26634/jes.1.1.1725 ◽

2012 ◽

Vol 1 (1) ◽

pp. 1-7

Author(s):

Vadim Geurkov ◽

◽

Lev Kirischian ◽

Keyword(s):

Mixed Signal ◽

Signal Systems

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Latch-Up Induced Slit Voiding in Aluminum Metal Lines

ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1999p0145 ◽

1999 ◽

Author(s):

Chunyu Zhang ◽

Lakshmi Vedula ◽

Shekhar Khandekar

Keyword(s):

High Temperature ◽

Line Width ◽

Fold Increase ◽

Metal Line ◽

Operating Life ◽

Mixed Signal ◽

Aluminum Metal ◽

Temperature Operating ◽

Latch Up

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

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Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0229 ◽

2016 ◽

Author(s):

Julien Goxe ◽

Béatrice Vanhuffel ◽

Marie Castignolles ◽

Thomas Zirilli

Keyword(s):

Electron Microscope ◽

Scanning Electron Microscope ◽

Sample Preparation ◽

Failure Analysis ◽

Focused Ion Beam ◽

Ion Beam ◽

Silicon On Insulator ◽

Mixed Signal ◽

Voltage Contrast ◽

Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

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