On combining pinpoint test set relaxation and run-length codes for reducing test data volume

This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

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Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 ◽

10.1109/vts.2001.923416 ◽

2002 ◽

Cited By ~ 143

Author(s):

A. Chandra ◽

K. Chakrabarty

Keyword(s):

Data Compression ◽

Test Data ◽

Test Data Compression ◽

Run Length ◽

System On A Chip

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Concurrent Core Test Based on Partial Test Set Reusing

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.529.359 ◽

2014 ◽

Vol 529 ◽

pp. 359-363

Author(s):

Xi Lei Huang ◽

Mao Xiang Yi ◽

Lin Wang ◽

Hua Guo Liang

Keyword(s):

Minimum Size ◽

Application Time ◽

Logical Circuit ◽

Test Set ◽

Test Cost ◽

Test Application ◽

Sharing Strategy ◽

Data Volume ◽

Set Sharing ◽

Test Sets

A novel concurrent core test approach is proposed to reduce the test cost of SoC. Before test, a novel test set sharing strategy is proposed to obtain a minimum size of merged test set by merging the test sets corresponding to cores under test (CUT).Moreover, it can be used in conjunction with general compression/decompression techniques to further reduce test data volume (TDV). During test, the proposed vector separating device which is composed of a set of simple combinational logical circuit (CLC) is designed for separating the vector from the merged test set to the correspondent test core. This approach does not add any test vector for each core and can test synchronously to reduce test application time (TAT). Experimental results for ISCAS’ 89 benchmarks have been rproven the efficiency of the proposed approach.

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