scholarly journals Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test

2005 ◽  
Author(s):  
Youhua Shi ◽  
S. Kimura ◽  
N. Togawa ◽  
M. Yanagisawa ◽  
T. Ohtsuki
Keyword(s):  
Power Consumption ◽  
Test Data ◽  
Run Length ◽  
Scan Test ◽  
Run Length Coding ◽  
Data Volume ◽  
Scan Chain

scholarly journals Test Data Compression with Alternating Equal-Run-Length Coding

2018 ◽  
Vol 7 (4.10) ◽  
pp. 1089
Author(s):  
Sivanantham S ◽  
Aravind Babu S ◽  
Babu Ramki ◽  
Mallick P.S
Keyword(s):  
Data Compression ◽  
Test Data ◽  
Average Power ◽  
Original Data ◽  
Test Data Compression ◽  
Run Length ◽  
Run Length Coding ◽  
Data Volume ◽  
Ic Testing ◽  
Repeated Runs

This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.  

scholarly journals Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

2010 ◽  
Vol E93-D (1) ◽  
pp. 10-16 ◽  
Author(s):  
Hiroyuki YOTSUYANAGI ◽  
Masayuki YAMAMOTO ◽  
Masaki HASHIZUME
Keyword(s):  
Test Data ◽  
Scan Test ◽  
Scan Chain ◽  
Chain Ordering

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

2015 ◽  
Vol 24 (06) ◽  
pp. 1550084 ◽  
Author(s):  
Haiying Yuan ◽  
Jiaping Mei ◽  
Xun Sun ◽  
K. T. Cheng ◽  
Kun Guo
Keyword(s):  
Power Consumption ◽  
Test Data ◽  
Application Time ◽  
Compression Method ◽  
Scan Testing ◽  
Run Length ◽  
Test Application Time ◽  
Test Application ◽  
Coding Method ◽  
Average Power Consumption

A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.

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